Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of dielectric layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out to form a first dielectric layer over the wiring lines and into the gaps between wiring lines. A PECVD step is carried out to deposit dielectric material over the first dielectric layer and within and to define a opening in the gap. A second HDPCVD step is carried out and the opening defined by the PECVD step is capped by a third dielectric layer. The method allows air-filled voids to be formed between adjacent metal wiring lines in a highly controlled manner which allows selection of the shape of the voids and precise location of the top of the voids. In addition, the voids are sealed by a denser and more durable material than is typical.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of three oxide layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out while keeping the substrate unbiased to form an oxide layer over the lines and in the gap. A second HDPCVD step in which the substrate is biased deposits a second oxide layer over the first oxide layer. During the second HDPCVD step some etching occurs and a portion of the first oxide layer is removed. A third HDPCVD step is carried out at a greater etch and sputtering rate than the second step to complete filling of the gap with dielectric material. The first oxide layer acts to protect the underlying structures from etching damage during the third step. Gaps between wiring lines can be filled with dielectric material without forming voids, even for high aspect ratio gaps.

Abstract: A retainer ring is provided for used on the polishing head of a CMP machine, which can allow the slurry being applied to the CMP process to be uniformly distributed over the surface of the wafer. The retainer ring is designed for use on a CMP machine of the type having a polishing table, a polishing pad, a polishing head for holding a semiconductor wafer retained in fixed position, and means for applying a mass of slurry to the wafer. The polishing head is of the type including an air-pressure means which can apply air pressure to a wafer loader used to hold the wafer in position. The retainer ring is formed with a plurality of straight grooves spaced at substantially equal intervals, each being radially inclined in such a manner so as to form an acute angle of attack against the slurry on the outside of said retainer ring when said retainer ring spins. Further, the retainer ring can be additionally formed with at least one circular groove intercrossing all of said straight grooves.

Abstract: The number of circuit path crossover points on boards mounting plural connected multichip modules is substantially reduced over the number that would otherwise be required. For 4-sided modules and boards, the modules are arranged on the board in such a way that their inter-connecting north-east-south-west ports are successively reordered to N-S-E-W. Additionally, further advantage in reducing crossover vias may be gained by combining the reordering with a phased rotation of the modules from their nominal congruent board position. For the 4-sided module, these expedients virtually eliminate crossover vias between the east and west ports. It also provides for all MCMs a ready common bus structure located at a common interior area of the mounting board, to which the E- and W-ports are oriented. The invention is applicable to a class of multi-sided, multi-chip modules on boards with a like number of sides.

Abstract: A new method of forming stress releasing voids within the intermetal dielectric of an integrated circuit is achieved. A first layer of patterned metallization is provided over semiconductor device structures in and on a semiconductor substrate. A silicon oxide layer is deposited overlying the first patterned metal layer. A silicon nitride layer is deposited over the silicon oxide layer. A metal layer is deposited over the silicon nitride layer and etched to form silicon nodules on the surface of the silicon nitride layer. The silicon nitride layer is etched away to the underlying silicon oxide layer wherein the silicon nitride under the silicon nodules remains in the form of pillars. The surface of the silicon oxide layer is coated with a spin-on-glass material which is baked and cured. The silicon nodules and silicon nitride pillars are removed, leaving voids within the spin-on-glass layer.

Abstract: A new method of forming stress releasing voids within the intermetal dielectric of an integrated circuit is achieved. A first layer of patterned metallization is provided over semiconductor device structures in and on a semiconductor substrate. A silicon oxide layer is deposited overlying the first patterned metal layer. A silicon nitride layer is deposited over the silicon oxide layer. A metal layer is deposited over the silicon nitride layer and etched to form silicon nodules on the surface of the silicon nitride layer. The silicon nitride layer is etched away to the underlying silicon oxide layer wherein the silicon nitride under the silicon nodules remains in the form of pillars. The surface of the silicon oxide layer is coated with a spin-on-glass material which is baked and cured. The silicon nodules and silicon nitride pillars are removed, leaving voids within the spin-on-glass layer.

Abstract: A new metallization method for metal lines formation of a very large scale integrated circuit (VLSI) is described. The metal lines are formed in a "wavy" or "snaky" pattern. It is a "wavy" pattern when the metal line goes through a vertically vibratory path. It is a "snaky" pattern when a metal line goes through a horizontally vibratory path. This includes both uniform and random "wavy" and "snaky" patterns. A metal line can also be formed in a pattern that is both "wavy" and "snaky." For the "wavy" pattern, the topography under the metal lines is fabricated using, for example, field oxide. The "wavelength" can vary from 1 to 10 micrometers. A slight modification of the metal mask can produce the "snaky" structure of the metal line. The stresses will be released by a small curvature change of the metal line. For the contact structures, a multi-contact layout with "wavy" structure can release more stress than can a single-contact layout of the same contact area.

Abstract: A new method of fabricating a convex charge coupled device is achieved. A silicon oxide layer is formed over the surface of a silicon substrate and patterned with a charge coupled device (CCD) electrode mask to provide openings to the silicon substrate. Nitride spacers are formed on the sidewalls of the openings. The integrated circuit is coated with a spin-on-glass layer. After curing, the spin-on-glass layer is etched back to expose the nitride spacers. Removing the nitride spacers leaves a second set of openings to the silicon substrate. Ions are implanted into the substrate through the second set of openings. The oxide layer is removed. The wafer is globally oxidized resulting in a thermal oxide layer with undulatory thickness. The thermal oxide is removed leaving a convex surface on the silicon substrate. A gate oxide layer is formed on the convex surface of the silicon substrate.

Abstract: A new method of local oxidation using a salicide recessed oxidation process is described. A thin silicon oxide layer is formed over the surface of a silicon substrate. A layer of silicon nitride is deposited overlying the silicon oxide layer. The silicon oxide and silicon nitride layers are patterned to provide openings exposing portions of the silicon substrate that will be oxidized subsequently. A metal layer is deposited overlying the silicon nitride layer and within the openings to the substrate. Channel-stops are ion implanted into the substrate through the openings. The salicide is formed by reacting the metal layer with the silicon substrate where the metal layer contacts the substrate within the openings. The metal silicide regions are removed, leaving recesses in the silicon surface within the openings. Field oxide regions are grown within the openings. Finally, the silicon nitride and silicon oxide layers are removed thereby completing local oxidation of the integrated circuit.