Abstract: A resistive memory device includes a first conductive line extending in a first horizontal direction on a substrate, a plurality of second conductive lines separated from the first conductive line in a vertical direction and extending in a second horizontal direction intersecting with the first horizontal direction, on the substrate, a plurality of memory cells respectively connected between the first conductive line and one second conductive line selected from among the plurality of second conductive lines at a plurality of intersection points between the first conductive line and the plurality of second conductive lines, each of the plurality of memory cells including a selection device and a resistive memory pattern, and a bottom electrode shared by the plurality of memory cells, the bottom electrode having a variable thickness in the first horizontal direction, and including a top surface having a concave-convex shape.

Abstract: A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.

Abstract: A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.

Abstract: A semiconductor device includes a lower insulating structure covering a circuit element on a semiconductor substrate and an upper structure on the lower insulating structure. The upper structure includes a memory cell structure between first and second conductive lines. The first conductive lines extend in a first horizontal direction, and the second conductive lines extend in a second horizontal direction. The memory cell structure includes at least three electrode patterns, a data storage material pattern, and a selector material pattern overlapping in a vertical direction. The selector material pattern includes a threshold switching material and a metal material. The threshold switching material includes germanium (Ge), arsenic (As), and selenium (Se), and the metal material includes at least one of tungsten (W), titanium (Ti), aluminum (Al), and copper (Cu). A content of the metal material is greater than 0 atomic % and less than 2 atomic %.

Abstract: A resistive memory device includes a first conductive line extending in a first horizontal direction on a substrate, a plurality of second conductive lines separated from the first conductive line in a vertical direction and extending in a second horizontal direction intersecting with the first horizontal direction, on the substrate, a plurality of memory cells respectively connected between the first conductive line and one second conductive line selected from among the plurality of second conductive lines at a plurality of intersection points between the first conductive line and the plurality of second conductive lines, each of the plurality of memory cells including a selection device and a resistive memory pattern, and a bottom electrode shared by the plurality of memory cells, the bottom electrode having a variable thickness in the first horizontal direction, and including a top surface having a concave-convex shape.

Abstract: A magnetic tunnel junction device and a manufacturing method therefor are provided. The magnetic tunnel junction device comprises: a seed layer having an FCC (001) crystal structure; a first ferromagnetic layer located on the seed layer and having perpendicular magnetic anisotropy; a tunneling barrier layer located on the first ferromagnetic layer; and a second ferromagnetic layer located on the tunneling barrier layer and having perpendicular magnetic anisotropy, wherein the first ferromagnetic layer has a BCC (001) crystal structure and does not have boron. Therefore, the magnetic tunnel junction device, which is structurally and thermally more stable, can be provided by using the seed layer configured to assist the crystal growth of a boron-free magnetic layer in a BCC (001) direction and provide perpendicular magnetic anisotropy thereto, that is, W2N or TaN which is a nitrogen-doped metal material having a cubic crystal structure and having a similar lattice constant to that of a magnetic layer material.

Abstract: A magnetic tunnel junction device and a manufacturing method therefor are provided. The magnetic tunnel junction device comprises: a seed layer having an FCC (001) crystal structure; a first ferromagnetic layer located on the seed layer and having perpendicular magnetic anisotropy; a tunneling barrier layer located on the first ferromagnetic layer; and a second ferromagnetic layer located on the tunneling barrier layer and having perpendicular magnetic anisotropy, wherein the first ferromagnetic layer has a BCC (001) crystal structure and does not have boron. Therefore, the magnetic tunnel junction device, which is structurally and thermally more stable, can be provided by using the seed layer configured to assist the crystal growth of a boron-free magnetic layer in a BCC (001) direction and provide perpendicular magnetic anisotropy thereto, that is, W2N or TaN which is a nitrogen-doped metal material having a cubic crystal structure and having a similar lattice constant to that of a magnetic layer material.

Abstract: Provided is a magnetic tunneling junction (MTJ) structure having (PMA). The MJT structure includes a seed layer including a tungsten-based substance, a first ferromagnetic layer that is positioned on the seed layer, includes a boron-based ferromagnetic material and has PMA, a tunneling barrier layer positioned on the first ferromagnetic layer, and a second ferromagnetic layer that is positioned on the tunneling barrier layer and has PMA, wherein the seed layer has a thickness in a range of 1 nm to 10 nm. Accordingly, by using the tungsten-based substance as a seed layer substance, the MTJ structure may be provided in which crystallinity of the first ferromagnetic layer is maintained even at a high temperature in a range of 350° C. to 400° C., a problem of the PMA reduction is prevented, and therefore, thermal stability is improved.