Patents by Inventor Ja-Hum Ku

Ja-Hum Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10651179
    Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-bae Park, Ja-hum Ku, Myeong-cheol Kim, Jin-wook Lee, Sung-kee Han
  • Patent number: 10134856
    Abstract: A semiconductor device includes an active fin partially protruding from an isolation pattern on a substrate, a gate structure on the active fin, a source/drain layer on a portion of the active fin adjacent to the gate structure, a source/drain layer on a portion of the active fin adjacent to the gate structure, a metal silicide pattern on the source/drain layer, and a plug on the metal silicide pattern. The plug includes a second metal pattern, a metal nitride pattern contacting an upper surface of the metal silicide pattern and covering a bottom and a sidewall of the second metal pattern, and a first metal pattern on the metal silicide pattern, the first metal pattern covering an outer sidewall of the metal nitride pattern. A nitrogen concentration of the first metal pattern gradually decreases according to a distance from the outer sidewall of the metal nitride pattern.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: November 20, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Da-Il Eom, Jeong-Ik Kim, Ja-Hum Ku, Chul-Sung Kim, Jun-Ki Park, Sang-Jin Hyun
  • Publication number: 20180277547
    Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.
    Type: Application
    Filed: May 30, 2018
    Publication date: September 27, 2018
    Inventors: Hong-bae PARK, Ja-hum KU, Myeong-cheol KIM, Jin-wook LEE, Sung-kee HAN
  • Patent number: 10014304
    Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: July 3, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-bae Park, Ja-hum Ku, Myeong-cheol Kim, Jin-wook Lee, Sung-kee Han
  • Patent number: 9613002
    Abstract: A processing method includes processing a wafer based on initial data, measuring errors for each of the plurality of areas, calculating an error similarity of at least some of the plurality of areas as a function of a separation distance between each pair of some of the areas, selecting a first area and a plurality of second areas adjacent to the first area, calculating weight values for the second areas based on the error similarities between each pair of second areas and the error similarities between the first area and each second area, calculating an estimated error of the first area based on the measured errors of the second areas and the weight values for the second areas, and generating estimated data based on the estimated errors for each of the plurality of areas.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: April 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Ho Han, Dae-Wook Kim, Jin-Young Lee, Sung-Won Choi, Byoung-Hoon Kim, Han-Hum Park, Sang-Jin Choi, Ja-Hum Ku
  • Publication number: 20170077248
    Abstract: A semiconductor device includes an active fin partially protruding from an isolation pattern on a substrate, a gate structure on the active fin, a source/drain layer on a portion of the active fin adjacent to the gate structure, a source/drain layer on a portion of the active fin adjacent to the gate structure, a metal silicide pattern on the source/drain layer, and a plug on the metal silicide pattern. The plug includes a second metal pattern, a metal nitride pattern contacting an upper surface of the metal silicide pattern and covering a bottom and a sidewall of the second metal pattern, and a first metal pattern on the metal silicide pattern, the first metal pattern covering an outer sidewall of the metal nitride pattern. A nitrogen concentration of the first metal pattern gradually decreases according to a distance from the outer sidewall of the metal nitride pattern.
    Type: Application
    Filed: September 1, 2016
    Publication date: March 16, 2017
    Inventors: Da-Il EOM, Jeong-Ik KIM, Ja-Hum KU, Chul-Sung KIM, Jun-Ki PARK, Sang-Jin HYUN
  • Publication number: 20170040328
    Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.
    Type: Application
    Filed: October 25, 2016
    Publication date: February 9, 2017
    Inventors: Hong-bae PARK, Ja-hum KU, Myeong-cheol KIM, Jin-wook LEE, Sung-kee HAN
  • Patent number: 9508727
    Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: November 29, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-bae Park, Ja-hum Ku, Myeong-cheol Kim, Jin-wook Lee, Sung-kee Han
  • Publication number: 20160133632
    Abstract: A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.
    Type: Application
    Filed: September 14, 2015
    Publication date: May 12, 2016
    Inventors: Hong-bae PARK, Ja-hum KU, Myeong-cheol KIM, Jin-wook LEE, Sung-kee HAN
  • Publication number: 20140229134
    Abstract: A processing method includes processing a wafer based on initial data, measuring errors for each of the plurality of areas, calculating an error similarity of at least some of the plurality of areas as a function of a separation distance between each pair of some of the areas, selecting a first area and a plurality of second areas adjacent to the first area, calculating weight values for the second areas based on the error similarities between each pair of second areas and the error similarities between the first area and each second area, calculating an estimated error of the first area based on the measured errors of the second areas and the weight values for the second areas, and generating estimated data based on the estimated errors for each of the plurality of areas.
    Type: Application
    Filed: October 30, 2013
    Publication date: August 14, 2014
    Inventors: Chang-Ho Han, DAE-WOOK KIM, JIN-YOUNG LEE, SUNG-WON CHOI, BYOUNG-HOON KIM, HAN-HUM PARK, SANG-JIN CHOI, JA-HUM KU
  • Publication number: 20120241874
    Abstract: A method for forming a gate stack of a semiconductor device comprises depositing a gate oxide layer on a channel region of a semiconductor substrate using chemical vapor deposition, atomic layer deposition or molecular layer deposition, depositing a nitride layer on the gate oxide layer, oxidizing the deposited nitride layer, depositing a high-K dielectric layer on the oxidized nitride layer, and forming a metal gate on the high-K dielectric layer.
    Type: Application
    Filed: March 25, 2011
    Publication date: September 27, 2012
    Inventors: BYUNG-DONG KIM, Ja-Hum Ku
  • Patent number: 8016941
    Abstract: A method and apparatus for crystallizing a semiconductor that includes a first layer having a first crystal lattice orientation and a second layer having a second crystal lattice orientation, comprising amorphizing at least a portion of the second layer, applying a stress to the second layer and heating the second layer above a recrystallization temperature.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: September 13, 2011
    Assignees: Infineon Technologies AG, Samsung Electronics Co., Ltd.
    Inventors: Matthias Hierlemann, Ja-Hum Ku
  • Patent number: 8008177
    Abstract: A method for fabricating a semiconductor device is provided using a nickel salicide process. The method includes forming a gate pattern and a source/drain region on a silicon substrate, forming a Ni-based metal layer for silicide on the silicon substrate where the gate pattern and the source/drain region are formed, and forming an N-rich titanium nitride layer on the Ni-based metal layer for silicide. Next, a thermal treatment is applied to the silicon substrate where the Ni-based metal layer for silicide and the N-rich titanium nitride layer are formed, thereby forming a nickel silicide on each of the gate pattern and the source/drain region. Then, the Ni-based metal layer for silicide and the N-rich titanium nitride layer are selectively removed to expose a top portion of a nickel silicide layer formed on the gate pattern and the source/drain region.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: August 30, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-chul San, Ja-hum Ku, Chul-sung Kim, Kwan-jong Roh, Min-joo Kim
  • Publication number: 20110163387
    Abstract: CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.
    Type: Application
    Filed: March 17, 2011
    Publication date: July 7, 2011
    Inventors: Kyoung Woo Lee, Ja Hum Ku, Taehoon Lee, Seung-Man Choi, Thomas W. Dyer
  • Patent number: 7911001
    Abstract: CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.
    Type: Grant
    Filed: July 15, 2007
    Date of Patent: March 22, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung Woo Lee, Ja Hum Ku, Taehoon Lee, Seung-Man Choi, Thomas W. Dyer
  • Patent number: 7816271
    Abstract: Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL.
    Type: Grant
    Filed: July 14, 2007
    Date of Patent: October 19, 2010
    Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation
    Inventors: Kyoung Woo Lee, Ja Hum Ku, WanJae Park, Chong Kwang Chang, Theodorus E. Standaert
  • Patent number: 7800134
    Abstract: Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: September 21, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-woo Lee, Ja-hum Ku, Jae-eon Park
  • Patent number: 7790622
    Abstract: Semiconductor fabrication processes are provided for removing sidewall spacers from gate structures while mitigating or otherwise preventing defect mechanisms such as damage to metal silicide structures or otherwise impeding or placing limitations on subsequent process flows.
    Type: Grant
    Filed: July 14, 2007
    Date of Patent: September 7, 2010
    Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation
    Inventors: Kyoung Woo Lee, Ja Hum Ku, Jun Jung Kim, Chong Kwang Chang, Min-Chul Sun, Jong Ho Yang, Thomas W. Dyer
  • Patent number: 7781276
    Abstract: A CMOS integrated circuit has NMOS and PMOS transistors therein and an insulating layer extending on the NMOS transistors. The insulating layer is provided to impart a relatively large tensile stress to the NMOS transistors. In particular, the insulating layer is formed to have a sufficiently high internal stress characteristic that imparts a tensile stress in a range from about 2 gigapascals (2 GPa) to about 4 gigapascals (4 GPa) in the channel regions of the NMOS transistors.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-woo Lee, Ja-hum Ku, Seung-man Choi
  • Patent number: 7781322
    Abstract: Provided are exemplary methods for forming a nickel silicide layer and semiconductor devices incorporating a nickel silicide layer that provides increased stability for subsequent processing at temperatures above 450° C. In particular, the nickel silicide layer is formed from a nickel alloy having a minor portion of an alloying metal, such as tantalum, and exhibits reduced agglomeration and retarded the phase transition between NiSi and NiSi2 to suppress increases in the sheet resistance and improve the utility for use with fine patterns. As formed, the nickel silicide layer includes both a lower layer consisting primarily of nickel and silicon and a thinner upper layer that incorporates the majority of the alloying metal.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ja-Hum Ku, Kwan-Jong Roh, Min-Chul Sun, Min-Joo Kim