Abstract: A semiconductor manufacturing equipment may include a process chamber for treating a substrate; a front-end module including a first transfer robot, wherein the first transfer robot may be configured to transport the substrate received in a container; a transfer chamber between the front-end module and the process chamber, wherein the transfer chamber may be configured to load or unload the substrate into or out of the process chamber; and a cassette capable of receiving a replaceable component capable of being used in the process chamber. The front-end module may include a seat plate configured to move in a sliding manner so as to retract or extend into or from the front-end module. The cassette may be configured to be loaded into the front-end module while the cassette is seated on the seat plate.

Abstract: The present disclosure relates to a photo-curable composition, a cured product thereof, and an optical member and a display device comprising same. The photo-curable composition has excellent low refractive index, light transmittance, and low haze characteristics by comprising a first olefinic monomer containing fluorine, a second olefinic monomer having an absolute viscosity of 7 cP or less at 25° C., a photo-polymerization initiator, and an amine compound.

Abstract: An ultrasonic image providing method of the present disclosure includes: receiving ultrasonic images; measuring a plurality of similarities for a plurality of measurement items for at least one of the ultrasonic images; comparing the plurality of similarities with corresponding default thresholds, respectively; when none of the plurality of similarities is greater than the corresponding default threshold, selecting a measurement item maintaining the greatest similarity among the plurality of similarities for a reference time; and providing an ultrasonic image for the selected measurement item as an ultrasonic image.

Abstract: According to an example embodiment, a semiconductor device includes a substrate having a cell array region and a peripheral circuit region. The substrate includes first active regions defined by a first trench isolation region in the cell array region, a second active region defined by a second trench isolation region in the peripheral circuit region, and at least one deep trench isolation region. The first active regions may be aligned to extend longitudinally in a first direction in the cell array region. The at least one deep trench isolation region is recessed in the substrate to a level lower than those of other points of a bottom surface of the second trench isolation region in the peripheral circuit region. The at least one deep trench isolation region includes at least one point that is spaced apart in the first direction from a corresponding one of the first active regions.

Abstract: Semiconductor devices are provided. The semiconductor devices may include an isolation pattern and first, second, and third active regions of a substrate. The first active region may be spaced apart from the second active region by a first width of the isolation pattern in a direction. A gate structure may be between the first and second active regions and may include a second width wider than the first width of the isolation pattern in the direction. Related methods of forming semiconductor devices are also provided.

Abstract: According to an example embodiment, a semiconductor device includes a substrate having a cell array region and a peripheral circuit region. The substrate includes first active regions defined by a first trench isolation region in the cell array region, a second active region defined by a second trench isolation region in the peripheral circuit region, and at least one deep trench isolation region. The first active regions may be aligned to extend longitudinally in a first direction in the cell array region. The at least one deep trench isolation region is recessed in the substrate to a level lower than those of other points of a bottom surface of the second trench isolation region in the peripheral circuit region. The at least one deep trench isolation region includes at least one point that is spaced apart in the first direction from a corresponding one of the first active regions.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate including first and second junction regions, a word line buried in the substrate, a bit line provided over the word line to cross the word line, a first contact provided between the substrate and the bit line and electrically connected to the first junction region, and a second contact provided between the bit lines and electrically connected to the second junction region. An overlapping area of a lower portion of the second contact may be greater than an overlapping area of an upper portion of the second contact with respect to the second junction region.

Abstract: Semiconductor devices are provided. The semiconductor devices may include an isolation pattern and first, second, and third active regions of a substrate. The first active region may be spaced apart from the second active region by a first width of the isolation pattern in a direction. A gate structure may be between the first and second active regions and may include a second width wider than the first width of the isolation pattern in the direction. Related methods of forming semiconductor devices are also provided.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate including first and second junction regions, a word line buried in the substrate, a bit line provided over the word line to cross the word line, a first contact provided between the substrate and the bit line and electrically connected to the first junction region, and a second contact provided between the bit lines and electrically connected to the second junction region. An overlapping area of a lower portion of the second contact may be greater than an overlapping area of an upper portion of the second contact with respect to the second junction region.

Abstract: Disclosed are a composite retardation plate, a composite polarizing plate including the same and a method for manufacturing the same. More particularly, a composite retardation plate is prepared by corona or plasma treatment of a face of a liquid crystal coating layer formed on a polymeric base film to improve adhesion therebetween and then directly providing a surface treatment coating layer above the coated film, thus being produced by a simple process without using a glass material while requiring neither an additional base material nor adhesive layer. Therefore, the retardation plate prepared as described above is desirably used as a retarder for a thin-film type display. The present invention also provides a composite polarizing plate including the above retardation plate and a method for manufacturing the foregoing.

Abstract: Provided are a method of fabricating a recess channel transistor and a related semiconductor device. The method may include forming a first gate trench on a substrate, forming a dielectric spacer on a sidewall of the first gate trench, forming a second gate trench on the substrate under the first gate trench, and forming a gate electrode to fill the trenches. The dielectric spacer may remain between the gate electrode and the substrate.

Abstract: Provided are a method of fabricating a recess channel transistor and a related semiconductor device. The method may include forming a first gate trench on a substrate, forming a dielectric spacer on a sidewall of the first gate trench, forming a second gate trench on the substrate under the first gate trench, and forming a gate electrode to fill the trenches. The dielectric spacer may remain between the gate electrode and the substrate.

Abstract: Some embodiments of the present invention provide semiconductor devices including a gate trench in an active region of a semiconductor substrate and a gate electrode in the gate trench. A low-concentration impurity region is provided in the active region adjacent to a sidewall of the gate trench. A high-concentration impurity region is provided between the low-concentration impurity region and the sidewall of the gate trench and along the sidewall of the gate trench. Related methods of fabricating semiconductor devices are also provided herein.