Abstract: One embodiment of the present invention is an arrangement for establishing connectivity between the inputs and outputs of n ports in a switching system includes first and second matrices of cross points and a control circuit. The first matrix includes n×n cross points, each first matrix cross point establishing a unilateral path between two of the n ports. The second matrix includes n×n cross points, each second matrix cross point establishing a unilateral path between two of the n ports. The control circuit is associated with a first cross point of the first matrix and a complementary cross point of the second matrix, the first cross point operable to establish a unilateral path from a source port (i) to the destination port (j), the complementary cross point operable to establish a unilateral path from the destination port (j) to the source port (i).

Abstract: A method for communicating from a source port (i) to a destination port (j) is employed within a switching system that has m ports, each of the ports being coupled to a local area network via a Hub. The connectivity between the inputs and outputs of the m ports forms a matrix of cross points having m rows and m columns. Each port has a transmit line coupled to a row of the matrix and a receive line coupled to a column of the matrix. A transmission operation from the source port (i) to the destination port (j) involves a first control circuit for unilaterally connecting the port (i) to the port (j), a second control circuit for unilaterally connecting the port (j) to the port (i). The method includes the use of a third control circuit, and a column control bus that couples the third control circuit to a plurality of control circuits including the second control circuit.

Abstract: A method for communicating information between a plurality of local area network sections having different transmission speeds includes three steps. One step includes receiving, within the physical layer protocol, a packet that is transmitted from a source terminal in a source network section having a source transmission speed to a destination terminal in a destination network section having a destination transmission speed, the destination transmission speed differing from the source transmission speed. Another step involves determining the transmission speed for the destination terminal. The method further includes the step of re-transmitting, within the physical layer protocol, the received packet to the destination network section at the destination transmission speed.

Abstract: A method for communicating from a source port (i) to a destination port (j) is employed within a switching system that has m ports, each of the ports being coupled to a local area network via a Hub. The connectivity between the inputs and outputs of the m ports forms a matrix of cross points having m rows and m columns. Each port has a transmit line being coupled to a row of the matrix and a receive line being coupled to a column of the matrix. A transmission operation from the source port (i) to the destination port (j) involves a first control circuit for unilaterally connecting the port (i) to the port (j) and a second control circuit for unilaterally connecting the port (i) to the port (i). The method comprises a first step of sending address information from the port (i) to a third control circuit.

Abstract: One embodiment of the present invention is an arrangement for establishing connectivity between the inputs and outputs of n ports in a switching system includes first and second matrices of cross points and a control circuit. The first matrix includes n×n cross points, each first matrix cross point establishing a unilateral path between two of the n ports. The second matrix includes n×n cross points, each second matrix cross point establishing a unilateral path between two of the n ports. The control circuit is associated with a first cross point of the first matrix and a complementary cross point of the second matrix, the first cross point operable to establish a unilateral path from a source port (i) to the destination port (j), the complementary cross point operable to establish a unilateral path from the destination port (j) to the source port (i).

Abstract: Local area networks are dynamically connected to one another by a switching system only when there is a packet to be exchanged between the two local area networks, otherwise the local area networks operate as separate and independent local area networks. The switching system can concurrently interconnect multi-pairs of local area networks together. The overall capacity of the local area networks interconnected via the switching system is increased since the local area networks operate free of other local area networks except when directly exchanging packets with another local area network. The switching system comprises a space switching unit and switch interface units with each switch interface unit interconnecting an individual local area network to the space switching unit.

Abstract: Allowing the implementation of a strictly nonblocking cross-point space switch central stage for the switching of SDH frames or other formats. The port terminating each incoming link has a time slot interchange (TSI) unit. Each TSI unit comprises incoming and outgoing sets of TSI's. The TSI's properly arrange each byte of each row of the STM-1 frame or other formats to be in the proper position for transmission on the STM-1 links. Within the STM-1 frame structure, each row of a frame is switched in an identical manner but the column designations within a row are switched differently. In response to rearranged frames from incoming TSI's, a cross-point switch is responsive to each column of each of the rows to switch each of the bytes of that column to the appropriate outgoing TSI for rearrangement and transmission on a STM-1 link.

Abstract: A clock recovery circuit for recovering the clock from an incoming data stream. The circuit comprises a transition detector and a module 3 counter operating at three times the expected rate of the incoming clock. A clock pulse is generated by the counter one count interval after a transition is detected.

Abstract: A packet switching system having separate arbitration and data buses together with circuitry for dividing the buses into a plurality of time segments termed phases. The plurality of phases permit a like plurality of separate arbitration operations and a like plurality of separate data exchanges to be effected concurrently on the arbitration bus and data bus, respectively. The use of n phases increases the data transmission capability of the system by a factor of n over prior art arrangements using only a single phase.

Abstract: This telephone switching system is comprised of a plurality of time slot interchangers (TSIs) which exchange information on an interleaved basis. The TSI's write and read this information in their associated port data store memories using common buses on a time shared basis. The interleaving permits faster call processing since the data store operates faster than its associated TSI and can therefore respond to read/write requests from a number of TSI's. The interleaving also permits each TSI processor to serve only certain types of calls, wherein each TSI may be equipped with a specialized processor adapted to serve a unique type of call such as conference, nonconference, data, etc.

Abstract: A vector generator (11) for a computer graphics system of the type in which the beam (26) of a CRT (13) is deflected by analogue deflexion signals to form an image comprised of a plurality of discrete vectors each defined, in each of two, orthogonal deflexion axes, the first and second digital words respectively defining the initial position and the length of the vector. The vector generator (11) includes circuitry (43, 44) that ensures that each vector is drawn with substantially uniform brightness regardless of the length of the vector. Additional circuitry (42, 54) is furnished so that an instantaneous indication may be obtained of a light pen (19) strike or the occurrence of edge violations. This circuitry (42, 54) also yields continuous digital information concerning the current beam position.