Abstract: The present invention describes methods and systems to perform hash algorithms as logic gate functions. It processes an N-bit block of data into the M-bit hash or message digest of the block in one (1) process cycle instead of the multiple cycles generally required. The minimum process time is the total propagation delay of an input block through the core logic for an implementing technology. A message requiring Y blocks to process would require no more than Y process (clock) cycles to produce the final hash value. This creates very simple and fast implementations of hash algorithms which enable them to be simply and easily integrated into any system.

Abstract: The present invention describes a method for implementing block encryption algorithms completely as non-sequential devices and systems. The method allows for encryption algorithms, using constant, or variable, key sizes, to be performed in one process (clock) cycle instead of the multiple cycles sequential designs require. This enables encryption devices and systems to operate significantly faster, and more simply, than sequential implementations. Thus, this invention allows encryption algorithms to be effectively performed as non-sequential logic gate functions.