Abstract: A computer system is provided in which asynchronously operating processing elements in the system are connected by means of an interconnection media so as to permit communication between an executing program on one of the processing elements with the memory on another processing element. Inter-processing communication logic located on each of the processing elements permits communication between executing programs on any one processing element. Inter-delivery support hardware is provided for interfacing between the interconnection media and the inter-processing communication logic.

Abstract: A data communication system contains a dual-port/dual-access-mode storage subsystem, and a communication controller connecting between that subsystem and external data communication channels. The storage subsystem includes one or more dual-port/dual-access mode storage devices consisting of a pair of random access and sequential access memory arrays, with a parallel block transfer connection between the arrays. The sequential access array can store a large block of up to N bytes (N for example equal to 256), and the random access array can store multiple such blocks. The subsystem also has RAM and SAM access ports respectively controllable in random access and sequential access modes and respectively connecting to the random access and sequential access arrays.