Patents by Inventor Jacek Dobaczewski

Jacek Dobaczewski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12361117
    Abstract: One or more computing devices, systems, and/or methods are provided. In an example, a method comprises storing an application image comprising a non-secure portion in a memory. A first debug request comprising a first target address is received. Halting of a processor is inhibited responsive to the first target address being within a protected region for a portion of non-secure code.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: July 15, 2025
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Jacek Dobaczewski, Yun-Lu Chen
  • Patent number: 12045181
    Abstract: One or more computing devices, systems, and/or methods are provided. In an example of the techniques presented herein, a system comprises a processor, a first interrupt source configured to generate a first non-secure interrupt, and an interrupt blocking unit configured to block the first non-secure interrupt responsive to the processor operating in a secure state.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: July 23, 2024
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Jacek Dobaczewski, Kuo-Jui Sun
  • Patent number: 12008106
    Abstract: Systems, methods, and devices authenticate operations for secured execution environments. Methods include performing, using one or more processing elements of a secured execution environment, a first cryptographic computation on a portion of code to generate a result. Methods also include determining, using the one or more processing elements, an authenticated version of a cryptographic value, the authenticated version of the cryptographic value being determined based on a signature computation and a second cryptographic computation that is an asymmetric cryptographic computation. Methods further include determining, using the one or more processing elements, if the result of the first cryptographic computation is verified based, at least in part, on a comparison with the authenticated version of the cryptographic value.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: June 11, 2024
    Assignee: Cypress Semiconductor Corporation
    Inventors: Victor Simileysky, Jacek Dobaczewski, Roman Baker
  • Patent number: 11928057
    Abstract: One or more computing devices, systems, and/or methods are provided. In an example, a method comprises storing a first application image and a second application image in an application image memory, designating the first application image as active, receiving a first address for accessing the application image memory from a processor, modifying the first address based on a first offset between a base starting address of the first application image and a starting physical address of the first application image in the application image memory to generate a second address, and accessing the application image memory using the second address.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: March 12, 2024
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventor: Jacek Dobaczewski
  • Publication number: 20230244779
    Abstract: One or more computing devices, systems, and/or methods are provided. In an example, a method comprises storing an application image comprising a non-secure portion in a memory. A first debug request comprising a first target address is received. Halting of a processor is inhibited responsive to the first target address being within a protected region for a portion of non-secure code.
    Type: Application
    Filed: August 22, 2022
    Publication date: August 3, 2023
    Inventors: Jacek DOBACZEWSKI, Yun-Lu CHEN
  • Publication number: 20230237156
    Abstract: One or more computing devices, systems, and/or methods are provided. In an example, a method comprises executing an application image to initialize a computing system. System state data associated with the initializing of the computing system is stored in a hardware register having at least one lockable until reset bit. A fault condition is identified responsive to the system state data not matching an expected value.
    Type: Application
    Filed: June 30, 2022
    Publication date: July 27, 2023
    Inventor: Jacek DOBACZEWSKI
  • Publication number: 20230236998
    Abstract: One or more computing devices, systems, and/or methods are provided. In an example of the techniques presented herein, a system comprises a processor, a first interrupt source configured to generate a first non-secure interrupt, and an interrupt blocking unit configured to block the first non-secure interrupt responsive to the processor operating in a secure state.
    Type: Application
    Filed: June 2, 2022
    Publication date: July 27, 2023
    Inventors: Jacek Dobaczewski, Kuo-Jui Sun
  • Publication number: 20230236962
    Abstract: One or more computing devices, systems, and/or methods are provided. In an example, a method comprises storing a first application image and a second application image in an application image memory, designating the first application image as active, receiving a first address for accessing the application image memory from a processor, modifying the first address based on a first offset between a base starting address of the first application image and a starting physical address of the first application image in the application image memory to generate a second address, and accessing the application image memory using the second address.
    Type: Application
    Filed: June 20, 2022
    Publication date: July 27, 2023
    Inventor: Jacek DOBACZEWSKI
  • Publication number: 20230117694
    Abstract: Systems, methods, and devices authenticate operations for secured execution environments. Methods include performing, using one or more processing elements of a secured execution environment, a first cryptographic computation on a portion of code to generate a result. Methods also include determining, using the one or more processing elements, an authenticated version of a cryptographic value, the authenticated version of the cryptographic value being determined based on a signature computation and a second cryptographic computation that is an asymmetric cryptographic computation. Methods further include determining, using the one or more processing elements, if the result of the first cryptographic computation is verified based, at least in part, on a comparison with the authenticated version of the cryptographic value.
    Type: Application
    Filed: October 14, 2021
    Publication date: April 20, 2023
    Applicant: Cypress Semiconductor Corporation
    Inventors: Victor Simileysky, Jacek Dobaczewski, Roman Baker