Patents by Inventor Jacek Lagowski

Jacek Lagowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11561254
    Abstract: Methods of characterizing electrical properties of a semiconductor layer structure on a wafer with topside semiconductor layers on an insulating or semi-insulating substrate, the semiconductor layer structure including a high electron mobility transistor (HEMT) heterostructure with a two-dimensional electron gas (2DEG) at a heterointerface between the semiconductor layers of the heterostructure. The methods include: (a) physically contacting the topside of the wafer within a narrow border zone at an edge of the wafer with a flexible metal cantilever electrode of a contacting device, wherein the flexible metal cantilever electrode contacts one or more of the semiconductor layers exposed at the narrow border zone so that the flexible metal cantilever electrode is in electrical contact with the 2DEG; and (b) applying corona charge bias and measuring a surface voltage of the semiconductor layers using a non-contact probe while maintaining the electrical contact with the 2DEG.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: January 24, 2023
    Assignee: SEMILAB Semiconductor Physics Laboratory Co., Ltd.
    Inventors: Marshall Wilson, Bret Schrayer, Alexandre Savtchouk, Dmitriy Marinskiy, Jacek Lagowski
  • Publication number: 20220381816
    Abstract: Methods of characterizing electrical properties of a semiconductor layer structure on a wafer with topside semiconductor layers on an insulating or semi-insulating substrate, the semiconductor layer structure including a high electron mobility transistor (HEMT) heterostructure with a two-dimensional electron gas (2DEG) at a heterointerface between the semiconductor layers of the heterostructure. The methods include: (a) physically contacting the topside of the wafer within a narrow border zone at an edge of the wafer with a flexible metal cantilever electrode of a contacting device, wherein the flexible metal cantilever electrode contacts one or more of the semiconductor layers exposed at the narrow border zone so that the flexible metal cantilever electrode is in electrical contact with the 2DEG; and (b) applying corona charge bias and measuring a surface voltage of the semiconductor layers using a non-contact probe while maintaining the electrical contact with the 2DEG.
    Type: Application
    Filed: May 27, 2021
    Publication date: December 1, 2022
    Inventors: Marshall Wilson, Bret Schrayer, Alexandre Savtchouk, Dmitriy Marinskiy, Jacek Lagowski
  • Patent number: 10969370
    Abstract: An example method of characterizing a semiconductor sample includes measuring an initial value, Vin, of a surface potential at a region of a surface of the semiconductor sample, biasing the semiconductor sample to have a target surface potential value (V0) of 2V or less, and depositing a monitored amount of corona charge (?Q1) on the region of the surface after adjusting the surface potential to the target value. The method also includes measuring a first value, V1, of the surface potential at the region after depositing the corona charge, determining the first change of surface potential (?V1=V1?V0), and determining the first capacitance value C1=?Q1/?V1, and characterizing the semiconductor sample based on V0, V1, ?V1, ?Q1 and C1.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: April 6, 2021
    Assignee: SEMILAB Semiconductor Physics Laboratory Co., Ltd.
    Inventors: Jacek Lagowski, Marshall Wilson, Alexandre Savtchouk, Carlos Almeida, Csaba Buday
  • Patent number: 10763179
    Abstract: An example semiconductor wafer includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, and a layer of the metal disposed on the dielectric layer. An example method of determining an effective work function of a metal on the semiconductor wafer includes determining a surface barrier voltage of the semiconductor wafer, and determining a metal effective work function of the semiconductor wafer based, at least in part, on the surface barrier voltage.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: September 1, 2020
    Assignee: SEMILAB Semiconductor Physics Laboratory Co., Ltd.
    Inventors: Dmitriy Marinskiy, Thye Chong Loy, Jacek Lagowski, Sung-Li Wang, Lin-Jung Wu, Shyh-Shin Ferng, Yi-Hung Lin, Sheng-Shin Lin
  • Publication number: 20180315630
    Abstract: A method for measuring charging of a semiconductor wafer associated with processing the semiconductor wafer includes using a probe assembly at a charge monitoring module to measure a charge on the semiconductor wafer prior to processing the semiconductor wafer using a processing tool, the probe assembly being located proximate to a processing station of the processing tool; transferring the semiconductor wafer from the charge monitoring module to the processing station using an automated wafer handling apparatus; processing the semiconductor wafer at the processing station using the processing tool; transferring the processed wafer from the processing station back to the charge monitoring module; using the probe assembly at the charge monitoring module to measure a charge on the semiconductor wafer after processing the wafer; and analyzing the measured charge on the semiconductor wafer both before and after processing the semiconductor wafer to determine information about charging of the wafer due to processi
    Type: Application
    Filed: May 1, 2018
    Publication date: November 1, 2018
    Inventors: Dmitriy Marinskiy, Andrew Findlay, Bret Schrayer, Jacek Lagowski, Piotr Edelman, Alexandre Savtchouk
  • Patent number: 9685906
    Abstract: Methods for fast and accurate mapping of passivation defects in a silicon wafer involve capturing of photoluminescence (PL) images while the wafer is moving, for instance, when the wafer is transported on a belt in a fabrication line. The methods can be applied to in-line diagnostics of silicon wafers in solar cell fabrication. Example embodiments include a procedure for obtaining the whole wafer images of passivation defects from a single image (map) of photoluminescence intensity, and can provide rapid feedback for process control.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: June 20, 2017
    Assignee: Semilab SDI LLC
    Inventors: Jacek Lagowski, Marshall D. Wilson, Ferenc Korsos, György Nádudvari
  • Publication number: 20160356750
    Abstract: An example method of characterizing a semiconductor sample includes measuring an initial value, Vin, of a surface potential at a region of a surface of the semiconductor sample, biasing the semiconductor sample to have a target surface potential value (V0) of 2V or less, and depositing a monitored amount of corona charge (?Q1) on the region of the surface after adjusting the surface potential to the target value. The method also includes measuring a first value, V1, of the surface potential at the region after depositing the corona charge, determining the first change of surface potential (?V1=V1?V0), and determining the first capacitance value C1=?Q1/?V1, and characterizing the semiconductor sample based on V0, V1, ?V1, ?Q1 and C1.
    Type: Application
    Filed: June 5, 2015
    Publication date: December 8, 2016
    Inventors: Jacek Lagowski, Marshall Wilson, Alexandre Savtchouk, Carlos Almeida, Csaba Buday
  • Publication number: 20160252565
    Abstract: An example semiconductor wafer includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, and a layer of the metal disposed on the dielectric layer. An example method of determining an effective work function of a metal on the semiconductor wafer includes determining a surface barrier voltage of the semiconductor wafer, and determining a metal effective work function of the semiconductor wafer based, at least in part, on the surface barrier voltage.
    Type: Application
    Filed: February 26, 2016
    Publication date: September 1, 2016
    Inventors: Dmitriy Marinskiy, Thye Chong Loy, Jacek Lagowski, Sung-Li Wang, Lin-Jung Wu, Shyh-Shin Ferng, Yi-Hung Lin, Sheng-Shin Lin
  • Publication number: 20150008952
    Abstract: Methods for fast and accurate mapping of passivation defects in a silicon wafer involve capturing of photoluminescence (PL) images while the wafer is moving, for instance, when the wafer is transported on a belt in a fabrication line. The methods can be applied to in-line diagnostics of silicon wafers in solar cell fabrication. Example embodiments include a procedure for obtaining the whole wafer images of passivation defects from a single image (map) of photoluminescence intensity, and can provide rapid feedback for process control.
    Type: Application
    Filed: June 26, 2014
    Publication date: January 8, 2015
    Inventors: Jacek Lagowski, Marshall D. Wilson, Ferenc Korsos, György Nádudvari
  • Patent number: 8912799
    Abstract: A method is described for accurate measuring of the excess carrier lifetime on a semiconductor sample from the carrier decay after termination of the excitation pulse imposed on the steady-state carrier excitation. The method includes determining a quality of decay parameter using progressing segments in each carrier decay; establishing an accurate lifetime measurement multiparameter domain for experimental variables whereby the quality of decay parameter falls within prescribed limits from the ideal exponential decay value of QD=1; and determining an excess carrier lifetime for the semiconductor sample based on experimental measurement conditions within the domain and the quality of decay value within the predetermined range indicative of an accurate excess carrier lifetime measurement.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: December 16, 2014
    Assignee: Semiconductor Physics Laboratory Co., Ltd.
    Inventors: Jacek Lagowski, Marshall D. Wilson
  • Patent number: 8093920
    Abstract: Surface photo-voltage measurements are used to accurately determine very long steady state diffusion length of minority carriers and to determine iron contaminant concentrations and other recombination centers in very pure wafers. Disclosed methods use multiple (e.g., at least two) non-steady state surface photovoltage measurements of diffusion length done at multiple (e.g., at least two) modulation frequencies. The measured diffusion lengths are then used to obtain a steady state diffusion length with an algorithm extrapolating diffusion length to zero frequency. The iron contaminant concentration is obtained from near steady state measurement of diffusion length at elevated frequency before and after iron activation. The concentration of other recombination centers can then be determined from the steady state diffusion length and the iron concentration measured at elevated frequency.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: January 10, 2012
    Assignee: Semiconductor Diagnostics, Inc.
    Inventors: Jacek Lagowski, Alexandre Savtchouk, Marshall D. Wilson
  • Publication number: 20100085073
    Abstract: Surface photo-voltage measurements are used to accurately determine very long steady state diffusion length of minority carriers and to determine iron contaminant concentrations and other recombination centers in very pure wafers. Disclosed methods use multiple (e.g., at least two) non-steady state surface photovoltage measurements of diffusion length done at multiple (e.g., at least two) modulation frequencies. The measured diffusion lengths are then used to obtain a steady state diffusion length with an algorithm extrapolating diffusion length to zero frequency. The iron contaminant concentration is obtained from near steady state measurement of diffusion length at elevated frequency before and after iron activation. The concentration of other recombination centers can then be determined from the steady state diffusion length and the iron concentration measured at elevated frequency.
    Type: Application
    Filed: August 21, 2009
    Publication date: April 8, 2010
    Inventors: Jacek Lagowski, Alexandre Savtchouk, Marshall D. Wilson
  • Publication number: 20090047748
    Abstract: Methods of measuring copper impurities on a silicon surface are disclosed. In certain embodiments, copper is electrically activated by ultra-violet illumination of the surface at room temperature. Activation can enhance the copper contribution to surface recombination and to surface voltage which are measured in a non-contact manner using a ac-surface photovoltage and a vibrating Kelvin-probe, respectively. Differential measurements before and after activation enable the separations of the copper impurities from other surface contaminants.
    Type: Application
    Filed: May 30, 2008
    Publication date: February 19, 2009
    Inventors: Alexandre Savtchouk, Jacek Lagowski, Lubomir L. Jastrzebski, Joseph Nicholas Kochey
  • Patent number: 7202691
    Abstract: A non-contact method is described for acquiring the accurate charge-voltage data on miniature test sites of semiconductor wafer wherein the test sites are smaller than 100 ?m times 100 ?m. The method includes recognizing the designated test site, properly aligning it, depositing a prescribed dose of ionic charge on the surface of the test site, and precise measuring of the resulting voltage change on the surface of the test site. The method further compromises measuring of the said voltage change in the dark and/or under strong illumination without interference from the laser beam employed in the Kelvin Force probe measurement of the voltage. The method enables acquiring of charge-voltage data without contacting the measured surface of the wafer and without contaminating the wafer. Thus, the measured wafer can be returned to IC fabrication line for further processing.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: April 10, 2007
    Assignee: Semiconductor Diagnostics, Inc.
    Inventors: Jacek Lagowski, Piotr Edelman, Dmitriy Marinskiy, Joseph Nicholas Kochey, Carlos Almeida
  • Publication number: 20060267622
    Abstract: A non-contact method is described for acquiring the accurate charge-voltage data on miniature test sites of semiconductor wafer wherein the test sites are smaller than 100 ?m times 100 ?m. The method includes recognizing the designated test site, properly aligning it, depositing a prescribed dose of ionic charge on the surface of the test site, and precise measuring of the resulting voltage change on the surface of the test site. The method further compromises measuring of the said voltage change in the dark and/or under strong illumination without interference from the laser beam employed in the Kelvin Force probe measurement of the voltage. The method enables acquiring of charge-voltage data without contacting the measured surface of the wafer and without contaminating the wafer. Thus, the measured wafer can be returned to IC fabrication line for further processing.
    Type: Application
    Filed: July 27, 2005
    Publication date: November 30, 2006
    Inventors: Jacek Lagowski, Piotr Edelman, Dmitriy Marinskiy, Joseph Kochey, Carlos Almeida
  • Patent number: 6815974
    Abstract: Techniques for determining the composition of mixed dielectric layers are disclosed.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: November 9, 2004
    Assignee: Semiconductor Diagnostics, Inc.
    Inventors: Jacek Lagowski, Marshall D. Wilson, John D'Amico, Alexandre Savtchouk, Lubomir L. Jastrzebski
  • Patent number: 6680621
    Abstract: A method is described for measuring the capacitance and the equivalent oxide thickness of an ultra thin dielectric layer on a silicon substrate in which the dielectric layer is uniform or patterned. The surface of a dielectric layer is electrically charged by a flux on ions from a corona discharge source until a steady state is reached when the corona flux is balanced by the leakage current across a dielectric. The flux is abruptly terminated and the surface potential of a dielectric is measured versus time. The steady state value of the surface potential is obtained by extrapolation of the potential decay curve to the initial moment of ceasing the corona flux. The thickness of a dielectric layer is determined by using the steady state potential or by using the value of the surface potential after a predetermined time.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: January 20, 2004
    Assignee: Semiconductor Diagnostics, Inc.
    Inventors: Alexander Savtchouk, Jacek Lagowski, John D'amico, Marshall D. Wilson, Lubomir L. Jastrzebski
  • Patent number: 6597193
    Abstract: A method is described for non-contact measuring the capacitance and the equivalent oxide thickness of ultra thin dielectric layer on a silicon substrate. The surface of a dielectric layer is electrically charged by a flux on ions from a corona discharge source until a steady state is reached when the corona flux is balanced by the leakage current across a dielectric. The flux is abruptly terminated and the surface potential of a dielectric is measured versus time. The steady state value of the surface potential is obtained by extrapolation of the potential decay curve to the initial moment of ceasing the corona flux. The thickness of a dielectric layer is determined by using the steady state potential or by using the value of the surface potential after a predetermined time. The method produces highly accurate results for oxide thickness below 40 Å with a demonstrated repeatability of a 0.03 Å in a series of 10 measurements.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: July 22, 2003
    Assignee: Semiconductor Diagnostics, Inc.
    Inventors: Jacek Lagowski, Alexander Savtchouk, Marshall D. Wilson
  • Patent number: 6538462
    Abstract: SILC characteristics and density of GOI defects of silicon wafers with thin dielectric films (e.g. SiO2) are determined using a non-contact method that does not require any test structures on the wafer. The method includes stressing a dielectric with a corona discharge and measuring the dielectric current-dielectric voltage (I-V) characteristics by monitoring under illumination the corona charge neutralization after stress. An I-V measurement done as function of corona fluence gives SILC characteristics of the wafer. The SILC characteristics are then compared at a constant dielectric field to provide a measure of GOI defect density. The I-V characteristic corresponding to low fluence that does not generate measurable SILC are used to determine a thickness of dielectric film.
    Type: Grant
    Filed: November 30, 1999
    Date of Patent: March 25, 2003
    Assignee: Semiconductor Diagnostics, Inc.
    Inventors: Jacek Lagowski, Marshall Wilson, Alexander Savtchouk
  • Patent number: 6512384
    Abstract: Minority carrier diffusion lengths are determined fast, accurately, and conveniently by illuminating a surface of the semiconductor with a beam composed of a plurality of light fluxes each having a different wavelength modulated at a different frequency. Surface photovoltages induced by different light fluxes are simultaneously detected by monitoring surface photovoltage signals at the different modulation frequencies. The surface photovoltage signals are frequency calibrated and then used to calculated a minority carrier diffusion length.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: January 28, 2003
    Assignee: Semiconductor Diagnostics, Inc.
    Inventors: Jacek Lagowski, Vladimir Faifer, Andrei Aleinikov