Patents by Inventor Jacek Wiatrowski

Jacek Wiatrowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8358551
    Abstract: A semiconductor memory storage device is disclosed. The semiconductor memory storage devices comprises: a plurality of data storage cells arranged in an array. The array comprises a plurality of columns and a plurality of rows, each column comprising at least one output line for outputting a data value from a data storage cell in a selected row of the column. Precharge circuitry for precharging the output lines to a predetermined voltage, the precharge circuitry comprising a plurality of switching devices corresponding to the plurality of columns each switching device controlled by a data output request signal and a power mode signal.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: January 22, 2013
    Assignee: ARM Limited
    Inventors: Jacek Wiatrowski, Martin Jay Kinkade, Yew Keong Chong
  • Patent number: 8014226
    Abstract: An integrated circuit memory 2 incorporates a first array of bit cells 4 and a second array of bit cells 6 with word line driver circuitry 8 disposed therebetween. Word line helper circuitry 18, 20 is disposed at the opposite edges of the array 4, 6 to the word line driver circuitry 8. The helper circuitry is responsive to the word line signal on a word line 12 being driven towards an asserted value to switch on and further drive the word line signal towards the asserted value. The helper circuitry is switched off by a global reset signal, which may be a self-timed global reset signal.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: September 6, 2011
    Assignee: ARM Limited
    Inventors: Gus Yeung, Amarnath Shanmugam, Yew Keong Chong, Jacek Wiatrowski
  • Publication number: 20110158021
    Abstract: A semiconductor memory storage device is disclosed. The semiconductor memory storage devices comprises: a plurality of data storage cells arranged in an array. The array comprises a plurality of columns and a plurality of rows, each column comprising at least one output line for outputting a data value from a data storage cell in a selected row of the column. Precharge circuitry for precharging the output lines to a predetermined voltage, the precharge circuitry comprising a plurality of switching devices corresponding to the plurality of columns each switching device controlled by a data output request signal and a power mode signal.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 30, 2011
    Applicant: ARM LIMITED
    Inventors: Jacek Wiatrowski, Martin Jay Kinkade, Yew Keong Chong
  • Publication number: 20110149674
    Abstract: An integrated circuit memory 2 incorporates a first array of bit cells 4 and a second array of bit cells 6 with word line driver circuitry 8 disposed therebetween. Word line helper circuitry 18, 20 is disposed at the opposite edges of the array 4, 6 to the word line driver circuitry 8. The helper circuitry is responsive to the word line signal on a word line 12 being driven towards an asserted value to switch on and further drive the word line signal towards the asserted value. The helper circuitry is switched off by a global reset signal, which may be a self-timed global reset signal.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 23, 2011
    Inventors: Gus Yeung, Amarnath Shanmugam, Yew Keong Chong, Jacek Wiatrowski
  • Patent number: 6894941
    Abstract: A row addressing circuit for DRAM memory is disclosed. Additional address or mode bits are used to dynamically select between long page and short page access modes, and to dynamically select between single cell per bit and dual, or two cell per bit modes in each memory bank within a memory block. In the short page access mode, only one wordline in a memory block is activated. In the long page access mode, two wordlines in the memory block are activated for accessing twice the number of bits as in short page access mode. In the single cell per bit mode, one bit of data is stored in one DRAM cell. In the two cell per bit mode, the row addressing circuit simultaneously activates two wordlines in a bank of the memory block to access one DRAM cell connected to each bitline of a pair of complementary bitlines for writing and reading complementary data. The row addressing circuit can combine the different access modes for system design flexibility.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: May 17, 2005
    Assignee: Atmos Corporation
    Inventors: Wlodek Kurjanowicz, Jacek Wiatrowski, Dariusz Kowalczyk, Greg Popoff
  • Publication number: 20030086316
    Abstract: A row addressing circuit for DRAM memory is disclosed. Additional address or mode bits are used to dynamically select between long page and short page access modes, and to dynamically select between single cell per bit and dual, or two cell per bit modes in each memory bank within a memory block. In the short page access mode, only one wordline in a memory block is activated. In the long page access mode, two wordlines in the memory block are activated for accessing twice the number of bits as in short page access mode. In the single cell per bit mode, one bit of data is stored in one DRAM cell. In the two cell per bit mode, the row addressing circuit simultaneously activates two wordlines in a bank of the memory block to access one DRAM cell connected to each bitline of a pair of complementary bitlines for writing and reading complementary data. The row addressing circuit can combine the different access modes for system design flexibility.
    Type: Application
    Filed: December 3, 2002
    Publication date: May 8, 2003
    Inventors: Wlodek Kurjanowicz, Jacek Wiatrowski, Dariusz Kowalczyk, Greg Popoff
  • Patent number: 6549483
    Abstract: A row addressing circuit for DRAM memory is disclosed. Additional address or mode bits are used to dynamically select between long page and short page access modes, and to dynamically select between single cell per bit and dual, or two cell per bit modes in each memory bank within a memory block. In the short page access mode, only one wordline in a memory block is activated. In the long page access mode, two wordlines in the memory block are activated for accessing twice the number of bits as in short page access mode. In the single cell per bit mode, one bit of data is stored in one DRAM cell. In the two cell per bit mode, the row addressing circuit simultaneously activates two wordlines in a bank of the memory block to access one DRAM cell connected to each bitline of a pair of complementary bitlines for writing and reading complementary data. The row addressing circuit can combine the different access modes for system design flexibility.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: April 15, 2003
    Assignee: ATMOS Corporation
    Inventors: Wlodek Kurjanowicz, Jacek Wiatrowski, Dariusz Kowalczyk, Greg Popoff
  • Publication number: 20020176311
    Abstract: A row addressing circuit for DRAM memory is disclosed. Additional address or mode bits are used to dynamically select between long page and short page access modes, and to dynamically select between single cell per bit and dual, or two cell per bit modes in each memory bank within a memory block. In the short page access mode, only one wordline in a memory block is activated. In the long page access mode, two wordlines in the memory block are activated for accessing twice the number of bits as in short page access mode. In the single cell per bit mode, one bit of data is stored in one DRAM cell. In the two cell per bit mode, the row addressing circuit simultaneously activates two wordlines in a bank of the memory block to access one DRAM cell connected to each bitline of a pair of complementary bitlines for writing and reading complementary data. The row addressing circuit can combine the different access modes for system design flexibility.
    Type: Application
    Filed: April 1, 2002
    Publication date: November 28, 2002
    Inventors: Wlodek Kurjanowicz, Jacek Wiatrowski, Dariusz Kowalczyk, Greg Popoff