Abstract: Relatively constant current sources and current mirrors are formed with vertical bipolar transistors operated in the inverse mode. In one embodiment of the invention, an integrated circuit current mirror includes a dual collector vertical NPN bipolar transistor having first and second regions of one conductivity type defining first and second collector regions, respectively, formed within a common third region of opposite conductivity type defining the base of the transistor. The third region is formed within a fourth region defining the emitter of the transistor. The structure of the dual collector vertical transistor is very compact since the two collectors share the same base region which is embedded in a common emitter (inverse collector) pocket. The "inverse" mode vertical transistor can function as a relatively constant current source with a voltage drop (VCEi) across its collector-to-emitter which is substantially less than that of a bipolar transistor operated in a normal mode.

Abstract: This invention contemplates the provision of a noise immune integrated circuit receiver in which the voltage reference to one side of an emitter-coupled current switch moves in response to the input signal, in a direction opposite the input signal. This provides the gate with a threshold hysteresis, making it immune to noise without requiring a large swing in input signal.

Abstract: CMOSFETs control the power in a bipolar logic gate to regulate its operating speed and hence its delay. In a specific embodiment of the invention, an n-channel CMOSFET controls the constant current through an emitter-coupled current switch, comprised of a pair of bipolar integrated circuit transistors. A p-channel CMOSFET, in series with each collector of the switch pair, establishes the collector voltage so as to maintain constant the output swing of the gate as the power through the gate is varied in order to regulate the gate delay. An error signal, indicative of factors that can cause variations in gate delay and the inverse of the error signal are generated by an on-chip circuit. The error signal is coupled to the n-channel CMOSFET and the inverse of the error signal is coupled to the p-channel CMOSFET. Thus, as the switch current is decreased in order to increase the gate delay, the collector impedance is simultaneously increased so the collector voltage, and hence the gate swing, remains constant.

Abstract: A high performance bipolar, field effect transistor (BiFET) logic circuit has minimal power supply requirements, allowing the circuit to be manufactured in higher density devices than current switched emitter follower (CSEF). BiFET logic circuit has a plurality of input lines and first and second output lines. A plurality of FET devices are connected in parallel each having a gate connected to a corresponding one of the input lines. Two bipolar transistors are connected as a differential pair, the parallel connection of said FET devices providing an input to the base of the first bipolar transistor while the base of the second bipolar transistor is supplied with a reference voltage. Output bipolar transistors connected as emitter followers drive the first and second output lines respectively.

Abstract: NOR logic performed by a half current switch emitter follower ("HCSEF") circuit utilizing a transistor operated in the inverse active mode as its current source and having logic levels compatible with those of current switch emitter follower ("CSEF") circuitry is combined with a novel reference bias generator that controls the logic low voltage level by controlling the voltage drop across the current source. The NOR.sub.i circuit utilizes less power than CSEF circuits, has a natural threshold equal to the threshold of CSEF circuits to which it is coupled, has a delay skew of approximately 1:1, and maintains minimum signal levels with respect to variations on V.sub.cc. The reference bias generator compensates for temperature, process variables and variations in the NOR.sub.i circuit and in the power supply.

Abstract: A logic redundancy circuit scheme, comprising a plurality of pairs of logic circuit groups, each logic circuit group in a given pair having a respective logic node and a respective power control line, with each logic circuit group in a given pair generating substantially the same logic function signal on its respective logic node as the other logic circuit group in the given pair generates on its respective logic node. The circuit scheme further includes a plurality of isolation circuits having respective output nodes, with a different isolation circuit connected to each different logic circuit group logic node. These isolation circuits are powered at all times and each operates to provide an output signal on its output node indicative of the signal on the logic node connected thereto, while isolating the connected logic node from nets connected to the isolation circuit output node.

Abstract: A BIFET logic circuit for quickly switching an output line from a high level to a reference level. The BICMOS circuit comprises a push-pull circuit including a first bipolar transistor for driving current into an output line, and a second bipolar transistor for sinking current from the output line; a CFET logic circuit for performing a logic function and including at least one N type FET for providing current to the base of the second bipolar transistor when a set of input lines to the CFET circuit has a first set of predetermined values; and a resistive means for connecting one of the source or drain of the at least one NFET to a power supply to provide a source of base current to the second bipolar transistor, even when the output line drops in voltage. This circuit is especially advantageous for driving low threshold CFET circuits.

Abstract: Disclosed is a Complementary Cascoded Logic (C.sup.2 L) Circuit which performs the AND-INVERT (AI) (or NAND) function. The AND function is implemented with input PNP transistors and the invert function is implemented with a first NPN transistor. An inverted NPN transistor serves as a current source for the first NPN. A first low voltage Schottky diode is serially connected between the emitter of the first NPN transistor and the emitter of the inverted NPN current source transistor. The first Schottky diode precludes, under certain conditions, simultaneous conduction of the first NPN transistor and the inverted transistor. Oppositely poled second and third low voltage Schottky diodes are utilized via an emitter follower output to provide an output voltage swing of V.sub.R .+-.V.sub.F, where V.sub.R is a reference voltage and V.sub.F is the potential drop across a Schottky diode. The low power high speed logic circuit (C.sup.2 L) has particular utility in redundant circuit applications.

Abstract: A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a degree of freedom for design of integrated circuits which is valuable. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitters of the selected region having the very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure.

Abstract: Compensation circuit means for inclusion in an off-chip driver circuit is provided to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips and the chips have a power supply and power leads respectively. The compensation circuit means, which is coupled across the output transistor circuit of the off-chip driver, may comprise one or more serially connected diodes. The diode (or diodes) may be formed by the base collector junction of a bipolar transistor.

Abstract: A driver circuit for a capacitively loaded line employs the charge storage capacitance of a diode for raising the base of a driver transistor above the circuit power supply voltage level so as to pull up the line to within a transistor base-emitter voltage drop of the power supply voltage level. The driver is easily fabricated in integrated circuit form, as no capacitors, either on or off chip, are required.The driver circuit includes a driver transistor, the collector of which is connected to the power supply and the emitter of which is connected to the line. A switching transistor has an input voltage applied between its base and emitter. A diode is connected between the switching and driver transistors, the anode being connected to the base of the driver transistor, and the cathode being connected to the collector of the switching transistor.

Abstract: A current controlled gate performing a NOR function utilizes a pair of transistors acting as current mirrors that receive a DC bias through a large resistor. This bias occurs when an input transistor is positive to insure that one of the current mirror transistors will saturate when the input transistors are "off" and the other will be driven into saturation when either of the input transistors is "on". When all inputs are negative, one of the current mirror transistors saturates thereby reducing the current to the input transistors effectively to zero. The saturation results in the collector-base capacitance increasing very rapidly such that the input assumes the characteristics of a common emitter due to the large capacitance existing in the collector of the current mirror transistor. An active push-pull output is produced with a single collector path from input to output.

Abstract: An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc. The on chip delay regulator accomplishes this by comparing a periodic reference signal to a periodic on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip. For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock).

Abstract: An on chip delay regulator circuit which varies the power in logic or array circuits on the chip so as to minimize, or eliminate, chip to chip circuit speed differences caused by power supply variations and/or lot to lot process differences, temperature, etc.The on chip delay regulator accomplishes this by comparing a reference signal to an on chip generated signal which is sensitive to power supply changes, lot to lot process changes, temperature, etc. The comparison creates an error signal which is used to change the power (current or voltage) supplied to the on chip circuits. By changing the circuit power, the circuit speed (gate delay) is increased or decreased as necessary to maintain a relatively constant circuit speed on each chip.For example, a plurality of integrated circuit chips each contain an on chip delay regulator. The on chip delay regulator on each chip of said plurality of integrated circuit chips receives and responds to the same signal (or clock).

Abstract: Heat is removed from a Large Scale Integrated Circuit semiconductor package via a thermal conductive path including a thermally conductive liquid. The integrated circuit chips are flip chip bonded to a substrate having a printed circuit and raised contact pads serving to interconnect contact areas on the chip. A metal, ceramic (or combination thereof) cover engages the perimeter of the substrate and encloses the chips (or chip). The thermal liquid is contained within the cavity define by the cover and substrate. The chips (or chip) and the flip chip connections are protected from contamination and the deleterious effects of the thermally conductive liquid by a parylene film enveloping same. Additionally, back side bonded (beam lead) integrated circuit chips will have an enhanced heat transfer path by incorporating liquid metal and a protective coating of parylene.