Patents by Inventor Jack A. Schroeder
Jack A. Schroeder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5742100Abstract: A flip-chip structure and method connects a semiconductor chip (11) having conductive bumps (16) to a substrate (12) having vias (19) extending from a first side (21) to a second side (18) of the substrate (12). A filler material (22) is deposited into the vias (19), and the conductive bumps (16) are inserted into the vias (19) for connecting the semiconductor chip (11) to a conductive element (17) covering the vias (19) on the second side (18) of the substrate (12).Type: GrantFiled: March 27, 1995Date of Patent: April 21, 1998Assignee: Motorola, Inc.Inventors: Jack A. Schroeder, Conrad S. Monroe
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Patent number: 4933747Abstract: An interconnect and cooling system has a housing which encloses a semiconductor device which is cooled by a pressurized coolant. The pressurized coolant exerts a force on the semiconductor device and holds it with a constant compressive force against a circuit board. Upon removal of the pressure the housing can be opened to easily and quickly replace the semiconductor device.Type: GrantFiled: March 27, 1989Date of Patent: June 12, 1990Assignee: Motorola Inc.Inventor: Jack A. Schroeder
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Patent number: 4933741Abstract: A multifunction ground plane for an electrical device such as an integrated circuit is provided by a plurality of conductors each having one end thereof adapted to be coupled to the electrical device with a ground plane adjacent and electrically isolated from said plurality of conductors. The ground plane includes a plurality of electrically isolated portions each of which can be coupled to the electrical device to provide operating potential and/or signals thereto or therefrom. The isolated ground plane portions have an impedance less than that of the electrical conductors and provide an alternate means for connecting operating potential(s) and/or operating signals to and from the electrical device while still functioning as a ground plane for the electrical conductors.Type: GrantFiled: November 14, 1988Date of Patent: June 12, 1990Assignee: Motorola, Inc.Inventor: Jack A. Schroeder
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Patent number: 4805007Abstract: A flip chip module including a film having solder receptor pads and interconnect lines to which a plurality of electronic devices and the like are bonded. The film is folded at predetermined areas thereby decreasing the size of this multichip device. A removable heat radiating cover is disposed over the film. This cover allows for both heat dissipation and easy access internal components for both testing and replacement after the flip chip module has been assembled.Type: GrantFiled: March 30, 1987Date of Patent: February 14, 1989Assignee: Motorola Inc.Inventor: Jack A. Schroeder
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Patent number: 4722914Abstract: An electronic module having a high density of silicon IC chips is provided by mounting the chips in tapered through-holes in a silicon substrate, filling the edge gaps between the chips and the substrate with a glass so that the chips, the filler glass, and the substrate have a smooth upper surface adapted to receive monolithic interconnections formed by planar metalization methods. The resulting assembly is enclosed in a housing also formed substantially from silicon, which contains electrically isolated pins for contacting the input-output electrodes of the assembly. Preferential etching is used to form the through-holes in the substrate as well as various alignment means on the substrate and other parts of the housing so that they are self-aligning during assembly. Improved performance, reliability, and low cost is obtained.Type: GrantFiled: August 13, 1986Date of Patent: February 2, 1988Assignee: Motorola Inc.Inventors: James E. Drye, Jack A. Schroeder, Vern H. Winchell, II
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Patent number: 4630096Abstract: An electronic module having a high density of silicon IC chips is provided by mounting the chips in tapered through-holes in a silicon substrate, filling the edge gaps between the chips and the substrate with a glass so that the chips, the filler glass, and the substrate have a smooth upper surface adapted to receive monolithic interconnections formed by planar metallization methods. The resulting assembly is enclosed in a housing also formed substantially from silicon, which contains electrically isolated pins for contacting the input-output electrodes of the assembly. Preferential etching is used to form the through-holes in the substrate as well as various alignment means on the substrate and other parts of the housing so that they are self-aligning during assembly. Improved performance, reliability, and low cost is obtained.Type: GrantFiled: May 30, 1984Date of Patent: December 16, 1986Assignee: Motorola, Inc.Inventors: James E. Drye, Jack A. Schroeder, Vern H. Winchell, II
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Patent number: 4613670Abstract: Water soluble dyestuffs having at least two reactive Lewis base sites are polymerized in a condensation reaction with group IVB metallocenes or group IVA organohalides to yield linear or crosslinked, and colored and/or fluorescent polymeric products. The polydyes are useful in providing permanent coloration of paper, plastics, textiles, paints and the like.Type: GrantFiled: May 3, 1984Date of Patent: September 23, 1986Assignee: Wright State UniversityInventors: Jack A. Schroeder, Charles E. Carraher, Jr., Richard A. Schwarz
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Patent number: 4513355Abstract: An improved VLSI device package and an improved method for contacting VLSI devices, in which the occurrences of wire bond shorts and lead voltage drops are substantially reduced, are obtained by providing multiple lead levels in the package, with the N.sub.2 leads on the upper lead level grouped into N.sub.3 bunches separated by N.sub.4 spaces, where each of the N.sub.4 spaces aligns with a bonding target on a corresponding one of the N.sub.1 leads on the lower level leads of the package, and where N.sub.1 <N.sub.2, preferably N.sub.1 .ltoreq.20 to 30% of N.sub.1 +N.sub.2. Wire bonds from the device to the N.sub.1 lower level leads align with the bonding targets, so that wire bonds from the device to the N.sub.2 upper level leads lie in clear corridors between the bonds to the N.sub.1 lower level leads. In this way wire bond crossovers and shorts are avoided. The N.sub.1 lower level leads can be made wide and short and are used for the high current connections.Type: GrantFiled: June 15, 1983Date of Patent: April 23, 1985Assignee: Motorola, Inc.Inventors: Jack A. Schroeder, Ernel R. Winkler
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Patent number: 4312981Abstract: Solubilized cellulosic material is modified through a condensation reaction with organotin halides. The modified products exhibit lower heats of combustion in air than unmodified cellulose, are hydrophobic and resistant to hydrolysis, and inhibit the growth of a variety of common fungi. The modified products are useful as insulation materials, mildew and mold resistant fabrics, and as material for topical bandages.Type: GrantFiled: April 1, 1980Date of Patent: January 26, 1982Assignee: Wright State UniversityInventors: Charles E. Carraher, Jr., David J. Giron, Jack A. Schroeder, Christy A. McNeely