Patents by Inventor Jack B. Dennis

Jack B. Dennis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130339977
    Abstract: Managing load in a set of multiple processing modules interconnected by an interconnection network includes: communicating with each of the processing modules in the set, from a load management unit, over respective communication channels that are independent from the interconnection network. In a memory of the load management unit, information is stored indicative of quantities of tasks assigned for execution by respective ones of the processing modules in the set. The load management unit communicates with processing modules in the set over the communication channels to request reassignment of tasks for execution by different processing modules based at least in part on the stored information.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 19, 2013
    Inventors: Jack B. Dennis, Xiao X. Meng
  • Publication number: 20130297877
    Abstract: A computing system comprises: one or more processors; and a memory system including one or more first level memories. Each first level memory is coupled to a corresponding one of the processors. Each processor is configured to execute instructions in an instruction set, at least some of the instructions in the instruction set accessing chunks of memory in the memory system. Each processor includes a plurality of storage locations, with at least some of the instructions each specifying a set of storage locations including: a first storage location in a first of the processors storing a unique identifier of a first chunk, and a second storage location in the first processor storing a reusable identifier of a storage area in the corresponding first level memory storing the first chunk.
    Type: Application
    Filed: May 1, 2013
    Publication date: November 7, 2013
    Inventor: Jack B. Dennis
  • Patent number: 8531955
    Abstract: One embodiment of the present invention prioritizes resource utilization in a multi-thread processor. A priority register stores thread information for P threads. The thread information includes P priority codes corresponding to the P threads, at least one of the P threads requesting use of at least one resource unit. A priority selector generates assignment signal to assign the at least one resource unit to the at least one of the P threads according to the P priority codes.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: September 10, 2013
    Assignee: The United States of America as Represented by the Secretary of the Navy
    Inventor: Jack B. Dennis
  • Publication number: 20090232154
    Abstract: One embodiment of the present invention prioritizes resource utilization in a multi-thread processor. A priority register stores thread information for P threads. The thread information includes P priority codes corresponding to the P threads, at least one of the P threads requesting use of at least one resource unit. A priority selector generates assignment signal to assign the at least one resource unit to the at least one of the P threads according to the P priority codes.
    Type: Application
    Filed: April 8, 2009
    Publication date: September 17, 2009
    Applicant: Government Agency - The United States of America as Represented By the Secretary of the Navy
    Inventor: Jack B. DENNIS
  • Publication number: 20090235258
    Abstract: One embodiment of the present invention performs peripheral operations in a multi-thread processor. A peripheral bus is coupled to a peripheral unit to transfer peripheral information including a command message specifying a peripheral operation. A processing slice is coupled to the peripheral bus to execute a plurality of threads. The plurality of threads includes a first thread sending the command message to the peripheral unit.
    Type: Application
    Filed: March 25, 2009
    Publication date: September 17, 2009
    Applicant: Government Agency - The United States of America as Represented By the Secretary of the Navy
    Inventors: Jack B. DENNIS, Sam B. SANDBOTE
  • Patent number: 7518993
    Abstract: One embodiment of the present invention prioritizes resource utilization in a multi-thread processor. A priority register stores thread information for P threads. The thread information includes P priority codes corresponding to the P threads, at least one of the P threads requesting use of at least one resource unit. A priority selector generates assignment signal to assign the at least one resource unit to the at least one of the P threads according to the P priority codes.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: April 14, 2009
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Jack B. Dennis
  • Patent number: 7512724
    Abstract: One embodiment of the present invention performs peripheral operations in a multi-thread processor. A peripheral bus is coupled to a peripheral unit to transfer peripheral information including a command message specifying a peripheral operation. A processing slice is coupled to the peripheral bus to execute a plurality of threads. The plurality of threads includes a first thread sending the command message to the peripheral unit.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: March 31, 2009
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Jack B. Dennis, Sam B. Sandbote
  • Patent number: 6195699
    Abstract: A real-time scheduler for scheduling periodic access to a shared resource by a number of channels. The channel period for each channel is represented by a channel value partitioned into an extra-fine value, a fine value, and a coarse value. The fine value is in units of access intervals, the length of time of each access. The coarse value is in units of scheduling periods, the maximum number of access intervals that can be represented by the fine value. The extra-fine value is in units of a number that evenly divides the access interval. During each scheduling period all non-zero coarse values are decremented by one and then if zero, indicate that the next cell send time for that channel falls in the next scheduling period. Concurrently, a fine process executes repeatedly in which all fine values that had a zero coarse value at the end of the previous scheduling period are compared to find the smallest value.
    Type: Grant
    Filed: November 3, 1998
    Date of Patent: February 27, 2001
    Assignee: Acorn Networks, Inc.
    Inventor: Jack B. Dennis
  • Patent number: 4814978
    Abstract: This invention provides a novel computer design that is capable of utilizing large numbers of very large scale integrated (VLSI) circuit chips as a basis for efficient high performance computation. This design is a static dataflow architecture of the type in which a plurality of dataflow processing elements communicate externally by means of input/output circuitry, and internally by means of packets sent through a routing network that implements a transmission path from any processing element to any other processing element. This design effects processing element transactions on data according to a distribution of instructions that is at most partially ordered. These instructions correspond to the nodes of a directed graph in which any pair of nodes connected by an arc corresponds to a predecessor-successor pair of instructions. Generally each predecessor instruction has one or more successor instructions, and each successor instruction has one or more predecessor instructions.
    Type: Grant
    Filed: July 15, 1986
    Date of Patent: March 21, 1989
    Assignee: Dataflow Computer Corporation
    Inventor: Jack B. Dennis
  • Patent number: 4153932
    Abstract: A processor is described which achieves highly parallel execution of programs represented in data-flow form. The language implemented incorporates conditional and iteration mechanisms, and the processor incorporates practical data-flow processing of a Fortran-level data-flow language. The processor has a unique architecture which avoids the problems of processor switching and memory/processor interconnection that usually limit the degree of realizable concurrent processing. The architecture offers an unusual solution to the problem of structuring and managing a two-level memory system.
    Type: Grant
    Filed: August 19, 1975
    Date of Patent: May 8, 1979
    Assignee: Massachusetts Institute of Technology
    Inventors: Jack B. Dennis, David P. Misunas
  • Patent number: 4149240
    Abstract: A digital computer may be structured in two separate sections, one of which performs the execution of arithmetic and conditional instructions, and the other which contains and performs operations upon data structures. The organization of the structure processing section of a digital computer is described herein. The structure processing section maintains data structures represented as acyclic directed graphs and is viewed as a functional unit by the instruction processing section; that is, instructions specifying structure operations are sent to the section, and any resulting values are returned to the instruction processing section. The organization of the structure processing section permits the simultaneous processing of many structure operations.
    Type: Grant
    Filed: June 14, 1976
    Date of Patent: April 10, 1979
    Assignee: Massachusetts Institute of Technology
    Inventors: David P. Misunas, Jack B. Dennis
  • Patent number: 4145733
    Abstract: A processor is described which achieves highly parallel execution of programs represented in data-flow form. The processor operates in a data-driven fashion; that is, an instruction of a program in the processor is enabled for execution upon the arrival of all required operands, and upon being executed, sends copies of the resulting value to all instructions which require it for their execution. The processor incorporates a form of deadlock prevention between the instructions of a data-flow program, allowing a value to be generated by an instruction and sent to the successor instructions in the computation only when those instructions are ready to receive the value. The incorporation of this mechanism prevents the possibility of conflict between successive stages of a pipelined computation and between successive iterations of an iterative computation.
    Type: Grant
    Filed: September 7, 1976
    Date of Patent: March 20, 1979
    Assignee: Massachusetts Institute of Technology
    Inventors: David P. Misunas, Jack B. Dennis
  • Patent number: 4130885
    Abstract: Packet communication is used in the architecture of a memory system capable of processing many independent memory transactions concurrently. The behavior of this memory system is prescribed by a formal memory model appropriate to a computer system for data flow programs.
    Type: Grant
    Filed: August 19, 1976
    Date of Patent: December 19, 1978
    Assignee: Massachusetts Institute of Technology
    Inventor: Jack B. Dennis
  • Patent number: 4128882
    Abstract: Packet communication is used in the architecture of a memory system having hierarchical structure. The behavior of this memory system is prescribed by a formal memory model appropriate to a computer system for data flow programs.
    Type: Grant
    Filed: August 19, 1976
    Date of Patent: December 5, 1978
    Assignee: Massachusetts Institute of Technology
    Inventor: Jack B. Dennis
  • Patent number: 3962706
    Abstract: This invention is a new concept for the organization of digital data processing apparatus, suitable for highly parallel execution of certain computations involving repeated patterns of computational operations. Possible applications include many types of signal processing computations such as filtering, modulation and waveform generation. The invention permits exploitation of the unique properties of asynchronous digital logic.
    Type: Grant
    Filed: March 29, 1974
    Date of Patent: June 8, 1976
    Assignee: Massachusetts Institute of Technology
    Inventors: Jack B. Dennis, David P. Misunas