Patents by Inventor Jack Chien

Jack Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11744665
    Abstract: A modular workspace platform system for providing a mobile work surface for a user includes a workspace platform attachable to a location specified by the user. The workspace platform includes a compact work surface for use in performing at least one manual task including temporarily storing a material, mixing two or more materials, temporarily supporting a tool, and providing a tool cleaning surface. In an embodiment, the compact work surface includes at least one of a trough, a tapered channel, a tool insertion slot, a wipe holder, a textured surface configured as the tool cleaning surface, a mixing surface a ruler holder, and a matrix ring holder.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: September 5, 2023
    Assignee: The Quick Co, LLC
    Inventors: Jack Chien Nguyen, Marc Andrew Hanchak, Peter Schuyler Livingston
  • Publication number: 20200253680
    Abstract: A modular workspace platform system for providing a mobile work surface for a user includes a workspace platform attachable to a location specified by the user. The workspace platform includes a compact work surface for use in performing at least one manual task including temporarily storing a material, mixing two or more materials, temporarily supporting a tool, and providing a tool cleaning surface. In an embodiment, the compact work surface includes at least one of a trough, a tapered channel, a tool insertion slot, a wipe holder, a textured surface configured as the tool cleaning surface, a mixing surface a ruler holder, and a matrix ring holder.
    Type: Application
    Filed: December 6, 2019
    Publication date: August 13, 2020
    Applicant: The Quick Co, LLC
    Inventors: Jack Chien Nguyen, Marc Andrew Hanchak, Peter Schuyler Livingston
  • Patent number: 8811271
    Abstract: In a satellite gateway, data is transmitted over a downstream channel at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. The downstream data is parsed to extract data packets. The data packets are then loaded into packet queues based on an identifier within such packets. The queues represent a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers that may also be based on the current signal quality at a subscriber location. The parsed data traffic is processed based on the profile of the plurality of profiles to produce processed data traffic, and transmitted from the packet queues over a downstream channel.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: August 19, 2014
    Assignee: Broadcom Corporation
    Inventors: Mark Dale, Anders Hebsgaard, David Hartman, Alan Kwentus, Steven Jaffe, Kelly Cameron, Stephen Krafft, Alan Gin, Jen-chieh (Jack) Chien, Dorothy Lin, Rocco Brescia, Joyce Wang
  • Publication number: 20130265870
    Abstract: In a satellite gateway, data is transmitted over a downstream channel at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. The downstream data is parsed to extract data packets. The data packets are then loaded into packet queues based on an identifier within such packets. The queues represent a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers that may also be based on the current signal quality at a subscriber location. The parsed data traffic is processed based on the profile of the plurality of profiles to produce processed data traffic, and transmitted from the packet queues over a downstream channel.
    Type: Application
    Filed: May 31, 2013
    Publication date: October 10, 2013
    Inventors: Mark Dale, Anders Hebsgaard, David Hartman, Alan Kwentus, Steven Jaffe, Kelly Cameron, Stephen Krafft, Alan Gin, Jen-chieh (Jack) Chien, Dorothy Lin, Rocco Brescia, Joyce Wang
  • Patent number: 8483122
    Abstract: In a DOCSIS based satellite gateway data is transmitted over a single downstream channel, at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. To accomplish this, the downstream DOCSIS MAC data is parsed to extract DOCSIS packets. The DOCSIS packets are then loaded into packet queues based on an identifier within such packets such as the MAC destination address or SID. Each of the queues represents a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers based on the current signal quality being experienced at the subscriber location. A PHY-MAP describing the downstream data structure to be transmitted and inserted into the downstream data. Data is extracted from the packet queues in queue blocks as defined by the PHY-MAP.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: July 9, 2013
    Assignee: Broadcom Corporation
    Inventors: Mark Dale, Hebsgaard Anders, David Hartman, Alan Kwentus, Steven Jaffe, Kelly Cameron, Stephen Krafft, Alan Gin, Jen-chieh (Jack) Chien, Dorothy Lin, Rocco Brescia, Joyce Wang
  • Publication number: 20100074167
    Abstract: In a DOCSIS based satellite gateway data is transmitted over a single downstream channel, at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. To accomplish this, the downstream DOCSIS MAC data is parsed to extract DOCSIS packets. The DOCSIS packets are then loaded into packet queues based on an identifier within such packets such as the MAC destination address or SID. Each of the queues represents a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers based on the current signal quality being experienced at the subscriber location. A PHY-MAP describing the downstream data structure to be transmitted and inserted into the downstream data. Data is extracted from the packet queues in queue blocks as defined by the PHY-MAP.
    Type: Application
    Filed: March 23, 2009
    Publication date: March 25, 2010
    Applicant: Broadcom Corporation
    Inventors: Mark Dale, Anders Hebsgaard, David Hartman, Alan Kwentus, Steven Jaffe, Kelly Cameron, Stephen Krafft, Alan Gin, Jen-chieh (Jack) Chien, Dorothy Lin, Rocco Brescia, Joyce Wang
  • Patent number: 7508785
    Abstract: In a DOCSIS based satellite gateway data is transmitted over a single downstream channel, at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. To accomplish this, the downstream DOCSIS MAC data is parsed to extract DOCSIS packets. The DOCSIS packets are then loaded into packet queues based on an identifier within such packets such as the MAC destination address or SID. Each of the queues represents a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers based on the current signal quality being experienced at the subscriber location. A PHY-MAP describing the downstream data structure to be transmitted and inserted into the downstream data. Data is extracted from the packet queues in queue blocks as defined by the PHY-MAP.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: March 24, 2009
    Assignee: Broadcom Corporation
    Inventors: Mark Dale, Anders Hebsgaard, David Hartman, Alan Kwentus, Steven Jaffe, Kelly Cameron, Stephen Krafft, Alan Gin, Jen-chieh (Jack) Chien, Dorothy Lin, Rocco Brescia, Joyce Wang
  • Publication number: 20070262434
    Abstract: An electronic component is disclosed including a plurality of semiconductor packages soldered together in a side-by-side configuration. The packages are batch processed on a substrate panel. The panel includes a plurality of through-holes drilled through the panel and subsequently filled with metal such as copper or gold. These filled through-holes lie along the cut line between adjacent packages so that, upon singulation, the filled through holes are cut and a portion of the filled through-holes are exposed at the side edges of the singulated packages. These exposed portions of the filled through-holes form vertical surface mount technology (SMT) pads. After the semiconductor packages are singulated and the SMT pads are defined in the side edges, SMT is used to solder the SMT pads of a first semiconductor package to the respective SMT pads of a second semiconductor package to structurally and electrically couple the two packages together side-by-side.
    Type: Application
    Filed: July 24, 2007
    Publication date: November 15, 2007
    Applicant: SANDISK CORPORATION
    Inventors: Chin-Tien Chiu, Cheemen Yu, Hem Takiar, Jack Chien, Meng-Ju Tsai
  • Publication number: 20070210444
    Abstract: A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 13, 2007
    Inventors: Che-Jung Chang, Chin-Tien Chiu, Cheemen Yu, Hem Takiar, Jack Chien, Ning Liu
  • Publication number: 20070158799
    Abstract: An electronic component is disclosed including a plurality of semiconductor packages soldered together in a side-by-side configuration. The packages are batch processed on a substrate panel. The panel includes a plurality of through-holes drilled through the panel and subsequently filled with metal such as copper or gold. These filled through-holes lie along the cut line between adjacent packages so that, upon singulation, the filled through holes are cut and a portion of the filled through-holes are exposed at the side edges of the singulated packages. These exposed portions of the filled through-holes form vertical surface mount technology (SMT) pads. After the semiconductor packages are singulated and the SMT pads are defined in the side edges, SMT is used to solder the SMT pads of a first semiconductor package to the respective SMT pads of a second semiconductor package to structurally and electrically couple the two packages together side-by-side.
    Type: Application
    Filed: December 29, 2005
    Publication date: July 12, 2007
    Inventors: Chin-Tien Chiu, Cheemen Yu, Hem Takiar, Jack Chien, Meng-Ju Tsai
  • Publication number: 20070108257
    Abstract: A semiconductor package having a low profile is disclosed. In embodiments, a surface mounted component may be mounted directly to the core of the semiconductor package substrate, so that there is no conductive layer, plating layers or solder paste between the component and the substrate core. The surface mounted component may be any type of component which may be surface mounted on a substrate according to an SMT process, including for example passive components and various packaged semiconductors.
    Type: Application
    Filed: November 16, 2005
    Publication date: May 17, 2007
    Inventors: Chih-Chin Liao, Ken Wang, Han-Shiao Chen, Chin-Tien Chiu, Jack Chien, Shrikar Bhagath, Cheemen Yu, Hem Takiar
  • Publication number: 20070096285
    Abstract: A semiconductor die substrate is disclosed for preventing delamination of the die and/or die cracking due to air bubbles trapped beneath the die, and a semiconductor package incorporating the substrate. A solder mask may be laminated on a surface of the substrate which is patterned with one or more passageways, or canals, allowing air bubbles to be expelled from beneath the semiconductor die during the semiconductor package fabrication. The canals may have a variety of shapes, including for example a wavy, undulating shape.
    Type: Application
    Filed: November 2, 2005
    Publication date: May 3, 2007
    Inventors: Chin-Tien Chiu, Jack Chien, Meng-Ju Tsai, Cheemen Yu, Hem Takiar
  • Publication number: 20040085976
    Abstract: In a DOCSIS based satellite gateway data is transmitted over a single downstream channel, at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. To accomplish this, the downstream DOCSIS MAC data is parsed to extract DOCSIS packets. The DOCSIS packets are then loaded into packet queues based on an identifier within such packets such as the MAC destination address or SID. Each of the queues represents a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers based on the current signal quality being experienced at the subscriber location. A PHY-MAP describing the downstream data structure to be transmitted and inserted into the downstream data. Data is extracted from the packet queues in queue blocks as defined by the PHY-MAP.
    Type: Application
    Filed: December 12, 2002
    Publication date: May 6, 2004
    Inventors: Mark Dale, Anders Hebsgaard, David Hartman, Alan Kwentus, Steven Jaffe, Kelly Cameron, Stephen Krafft, Alan Gin, Jen-Chieh (Jack) Chien, Dorothy Lin, Rocco Brescia, Joyce Wang