Abstract: A memory block with any source alignment is streamed into general-purpose registers (GPRs) as aligned data using a streaming load instruction. A streaming store instruction reads the aligned data from the GPRs and writes the data into memory with any destination alignment. Data is streamed from any source alignment to any destination alignment. Memory accesses are aligned to memory lines. The data is rotated using the offset within a memory line of the base address. The rotated data is stored in a scratch register for use by the next streaming load instruction. Rotated data just read from memory is combined with rotated data in the scratch register read by the last streaming load instruction to generate result data to load into the destination GPR. Streaming condition codes are set when the block's end is detected to disable future streaming instructions. Aligned memory accesses at full bandwidth read the un-aligned block.

Abstract: A method of efficiently coordinating the communication of data and commands between multiple entities in a system is disclosed. A transaction protocol enabling centralized scheduling of chains of data transfers in a system is disclosed.

Abstract: The invention relates to the field of system on a chip, SoC, information processing architecture and particularly to the use of a homogenous, concurrent-communication interconnection architecture that allows a variety of different functions to be connected together and their full synergistic performance realized. The functions are decoupled from each other, allowing performance optimization of each function without regard for the other functions on the chip. The system data flow is coordinated using a overall system schedule allowing data interactions to be orchestrated efficiently.

Abstract: Penalty for taking branch in pipelined processor is reduced by pre-calculating target of conditional branch before branch is encountered, thereby effectively converting branches to jumps. During program execution, pipeline penalty is reduced effectively to that of unconditional jump. Offset bits are replaced in a conditional branch with index bits based on addition of offset bits and a program counter value. Scheme reduces need for cycle to calculate target of taken branch. Scheme may be applied during cache fill or dead cycle when taken branch is read from pipelined cache.

Abstract: In complex systems, the arrival of data to a computation component is difficult to predict. A method of synchronizing the initiation of computation with the reception of its input data is disclosed. The method allows the input data and computation initiation commands to arrive in any order. The method is dynamically adjustable allowing for varying numbers of data inputs.

Abstract: A microprocessor capable of processing at least two program instructions at the same time and capable of issuing the two program instructions to two symmetrical multifunctional program execution units. The microprocessor includes a plurality of registers which store a plurality of operands and an instruction issue control which controls issuance of program instructions to the two symmetrical multifunctional program execution units. The instruction issue control issues the two program instructions (e.g. first and second) without decoding them in order to determine the processing functions required to be performed in response to the two program instructions.

Abstract: A microprocessor capable of processing at least two program instructions at the same time and capable of issuing the two program instructions to two symmetrical multifunctional program execution units. The microprocessor includes a plurality of registers which store a plurality of operands and an instruction issue control which controls issuance of program instructions to the two symmetrical multifunctional program execution units. The instruction issue control issues the two program instructions (e.g. first and second) without decoding them in order to determine the processing functions required to be performed in response to the two program instructions.

Abstract: A microprocessor capable of processing at least two program instructions at the same time and capable of issuing the two program instructions to two symmetrical multifunctional program execution units. The microprocessor includes a plurality of registers which store a plurality of operands and an instruction issue control which controls issuance of program instructions to the two symmetrical multifunctional program execution units. The instruction issue control issues the two program instructions (e.g. first and second) without decoding them in order to determine the processing functions required to be performed in response to the two program instructions.