Patents by Inventor Jack Chui

Jack Chui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8013632
    Abstract: Integrated circuits such as programmable logic devices are provided with hotsocket detection circuitry. The hotsocket detection circuitry monitors signals on data pins and power supply voltages. If the data pins become active before the power supply voltages have reached appropriate levels, a hotsocket condition is identified. When a hotsocket condition is identified, driver circuitry on the integrated circuit can be disabled by a hotsocket signal. The integrated circuit may include multiple blocks of input-output circuitry, each of which includes a local hotsocket circuit that uses global hotsocket and power-on-reset signals in disabling input-output circuitry in that input-output block. A power supply circuit in each input-output block may ensure that the local hotsocket circuit in that input-output block is powered.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: September 6, 2011
    Assignee: Altera Corporation
    Inventors: Jack Chui, Linda Chu, Toan D. Do
  • Patent number: 7893716
    Abstract: Hotsocket detection circuitry is provided for detecting hotsocket conditions in integrated circuits such as programmable logic device integrated circuits. Power-on-reset circuitry may provide a power-on-reset signal that is indicative of when power supply voltages are ready to power circuitry on the integrated circuit for normal operation. A delay circuit that is powered by a power supply voltage may receive the power-on-reset signal and may generate a corresponding delayed version of the power-on-reset signal. The delayed version of the power-on-reset signal may be provided to the hotsocket detection circuitry to ensure that the hotsocket detection circuitry produces a hotsocket signal that transitions after a transition in the power-on-reset signal. The delay circuit may include one or more inverter stages.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: February 22, 2011
    Assignee: Altera Corporation
    Inventors: Jack Chui, Toan D. Do, Kok Siong Tee
  • Patent number: 7884644
    Abstract: A level shifter circuit includes first and second transistors that receive a first input signal at control inputs. A level shifted output signal is generated by the first and the second transistors. Third and fourth transistors receive a second input signal at control inputs. The first input signal is an inverse of the second input signal. A first multiplexer circuit is configurable to couple a control input of a fifth transistor to the first and the second transistors. A second multiplexer circuit is configurable to couple a control input of a sixth transistor to the third and the fourth transistors.
    Type: Grant
    Filed: February 21, 2010
    Date of Patent: February 8, 2011
    Assignee: Altera Corporation
    Inventors: Luqiong Wu, Linda Chu, Toan D. Do, Jack Chui, Praveen Krishnanunni