Abstract: A processor having an embedded cache memory, the cache including a tag array that is split into first and second halves each having N ways, the first half storing an upper M sets and the second half storing a lower M sets. Lower order linear address bits read the first and second halves in a first phase of a clock cycle. Compare circuitry compares each of the N ways read out of both the first and second halves of the tag array with higher order physical address bits. Select circuitry then selects one of two sets of way select signals based on a higher order linear address bit. A data array having N ways and 2M sets is accessed by the lower order linear address bits in combination with the higher order linear address bit, with the selected set of way select signals outputting data of the correct way.