Patents by Inventor Jack D. Parrish

Jack D. Parrish has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5366916
    Abstract: A process for fabricating a high voltage CMOS transistor having a non-self aligned implanted channel which permits the operation of the device at high voltages. The non-self aligned implanted channel does not require alignment with the gate electrode of the CMOS device, but is accurately implanted early in the fabrication of the device through reliance on direct wafer stepper technology. As a result, the non-self aligned implanted channel does not require a high temperature drive, such that fabrication of the transistor is compatible with VLSI and ULSI processes, and the transistor can be up-integrated onto logic integrated circuits. Accuracy of the placement of the non-self aligned implanted channel provides for a shorter channel length, which enables the device to be highly area efficient while also increasing the current capability of the device.
    Type: Grant
    Filed: February 4, 1993
    Date of Patent: November 22, 1994
    Assignee: Delco Electronics Corporation
    Inventors: Richard A. Summe, Randy A. Rusch, Douglas R. Schnabel, Jack D. Parrish
  • Patent number: 5047358
    Abstract: A process for forming both low voltage CMOS transistors and high voltage CMOS transistors on a common integrated circuit chip uses a common implantation and drive-in step to form both the n-type well of each PMOS transistor and the n-type drain extension well of each lightly doped drain (LDD) NMOS transistor and a separate implant and drive-in to form the p-type drain extension well of each LDD PMOS transistor.
    Type: Grant
    Filed: March 17, 1989
    Date of Patent: September 10, 1991
    Assignee: Delco Electronics Corporation
    Inventors: Walter K. Kosiak, Douglas R. Schnabel, Jonathan D. Mann, Jack D. Parrish, Paul R. Rowlands, III
  • Patent number: 4918026
    Abstract: A process is used to form in a common substrate a PMOS transistor of the lightly doped drain (LDD) type, an NMOS transistor of the LDD type and a vertical n-p-n bipolar transistor. In particular: the steps used to form an n-type well for the PMOS transistor, and an n-type drain extension well for the NMOS transistor, are also used to form the n-type collector of the bipolar transistor; the steps used to form the p-type extension well for the PMOS transistor are also used to form the p-type base of the bipolar transistor, the source/drain implantation step for the NMOS transistor is also used to form the emitter and a contact region for the collector of the bipolar transistor; and the source/drain implantation step for the PMOS transistor is used to form a contact region for the base of the bipolar transistor.
    Type: Grant
    Filed: March 17, 1989
    Date of Patent: April 17, 1990
    Assignee: Delco Electronics Corporation
    Inventors: Walter K. Kosiak, Douglas R. Schnabel, Jonathan D. Mann, Jack D. Parrish, Paul R. Rowlands, III