Patents by Inventor Jack David Flicker

Jack David Flicker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12218497
    Abstract: A disclosed switching apparatus, such as a circuit breaker, includes a transistor switch circuit connected between a power input terminal and a load terminal, and, connected to the power input terminal and bypassing the transistor switch circuit, a switchable bypass leg that is optically switched by a series-connected photoconductive semiconductor switch (PCSS). The transistor switch circuit includes at least one cascade of three or more series-connected transistors, and at least one resistor network configured to divide a voltage from a voltage source across a cascade of series-connected transistors. Operating the switch apparatus includes detecting whether a sensed electric current is in a fault condition, opening the transistor switch circuit upon detecting a fault condition, and then closing the PCSS so that the electric current is diverted onto a switchable bypass path. The opening of the transistor switch circuit comprises turning OFF a normally-ON transistor switch circuit.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: February 4, 2025
    Assignees: National Technology & Engineering Solutions of Sandia, LLC, UNM Rainforest Innovations
    Inventors: Gregory Pickrell, Jason Christopher Neely, Lee Gill, Jacob Mueller, Luciano Andres Garcia Rodriguez, Jack David Flicker, Emily Ann Schrock, Robert Kaplar, Harold P. Hjalmarson, Jane Lehr
  • Patent number: 12218255
    Abstract: A vertical gallium nitride (GaN) PN diode uses epitaxial growth of a thick drift region with a very low carrier concentration and a carefully designed multi-zone junction termination extension to achieve high voltage blocking and high-power efficiency. An exemplary large area (1 mm2) diode had a forward pulsed current of 3.5 A, an 8.3 m?-cm2 specific on-resistance, and a 5.3 kV reverse breakdown. A smaller area diode (0.063 mm2) was capable of 6.4 kV breakdown with a specific on-resistance of 10.2 m?-cm2, when accounting for current spreading through the drift region at a 45° angle.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: February 4, 2025
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Luke Yates, Brendan P. Gunning, Mary H. Crawford, Jeffrey Steinfeldt, Michael L. Smith, Vincent M. Abate, Jeramy R. Dickerson, Andrew M. Armstrong, Andrew Binder, Andrew A. Allerman, Robert J. Kaplar, Jack David Flicker, Gregory W. Pickrell
  • Patent number: 12196784
    Abstract: A method and system for determining the state of one or both of an electrical conductor or an associated system utilizing a non-invasive sensor and a magnetostrictive response from the current of the electrical conductor. The method includes providing a sensor assembly including a magnetostrictive resonator sensor and a signal detector. A state of one or both of the electrical conductor or the associated system is determined with the fault detector in response to a first frequency profile and a second frequency profile obtained with the magnetostrictive resonator sensor. A fault monitoring system utilizing a magnetostrictive resonator sensor is also disclosed.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: January 14, 2025
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Sigifredo Gonzalez, Jack David Flicker, Todd Monson, Eric Langlois, Nicholas Sonny Gurule, Olga Lavrova
  • Publication number: 20220165888
    Abstract: A vertical gallium nitride (GaN) PN diode uses epitaxial growth of a thick drift region with a very low carrier concentration and a carefully designed multi-zone junction termination extension to achieve high voltage blocking and high-power efficiency. An exemplary large area (1 mm2) diode had a forward pulsed current of 3.5 A, an 8.3 m?-cm2 specific on-resistance, and a 5.3 kV reverse breakdown. A smaller area diode (0.063 mm2) was capable of 6.4 kV breakdown with a specific on-resistance of 10.2 m?-cm2, when accounting for current spreading through the drift region at a 45° angle.
    Type: Application
    Filed: January 10, 2022
    Publication date: May 26, 2022
    Inventors: Luke Yates, Brendan P. Gunning, Mary H. Crawford, Jeffrey Steinfeldt, Michael L. Smith, Vincent M. Abate, Jeramy R. Dickerson, Andrew M. Armstrong, Andrew Binder, Andrew A. Allerman, Robert J. Kaplar, Jack David Flicker, Gregory W. Pickrell
  • Patent number: 11227844
    Abstract: A GaN diode EMP arrestor exhibits breakdown in <10 ns at reverse-bias voltage >20 kV. Additionally, the arrestor exhibits avalanche ruggedness at 1 kA/cm2 in a 1 mm2 device (i.e. 10 A absolute current) over a period of 500 ns following the onset of breakdown. Finally, the specific on-resistance in the forward direction is <20 m? cm2.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: January 18, 2022
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Robert Kaplar, Jack David Flicker, Olga Lavrova
  • Patent number: 10886841
    Abstract: A hybrid switched capacitor power converter for high-power applications is provided. The converter has a transistor-switched input-stage boost converter followed by a capacitor-and-diode ladder circuit. The converter is adapted to produce an output voltage of at least 5 kV at a power level of at least 0.5 kW. The ladder circuit includes one or more multi-stage rails.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: January 5, 2021
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Robert W. Brocato, Jason C. Neely, Lee Joshua Rashkin, Jarod James Delhotal, Jack David Flicker, Robert Kaplar, Joshua Stewart, James Richards
  • Patent number: 10084310
    Abstract: A DC power bus having reduced parasitic inductance and higher tolerable operating temperature is disclosed. In example embodiments, a bus structure overlies a printed circuit board, and an array of capacitors is arranged on a surface of the printed circuit board distal the bus structure. The bus structure comprises an upper metal plate, a lower metal plate, and a dielectric film interposed between the upper and lower metal plates. The capacitors are connected in parallel between conductive planes of the printed circuit board. The upper and lower metal plates of the bus structure are connected to respective conductive planes of the printed circuit board.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: September 25, 2018
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Jason C. Neely, Joshua Stewart, Jarod James Delhotal, Jack David Flicker, Geoff L. Brennecka