Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract: Apparatus and computing systems associated with data pre-fetching are described. One embodiment includes a processor that includes a first unit to store data corresponding to a load instruction and an instruction pointer (IP) value associated with the load instruction. The processor also includes a second unit to produce a predicted demand address for a next load instruction, the predicted demand address being based on a constant stride value. The processor also includes a third unit to generate an instruction pointer pre-fetch (IPP) request for the predicted demand address. The processor may also include units to arbitrate between generated IP pre-fetch requests and alternative pre-fetch requests.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract: Apparatus and computing systems associated with data pre-fetching are described. One embodiment includes a processor that includes a first unit to store data corresponding to a load instruction and an instruction pointer (IP) value associated with the load instruction. The processor also includes a second unit to produce a predicted demand address for a next load instruction, the predicted demand address being based on a constant stride value. The processor also includes a third unit to generate an instruction pointer pre-fetch (IPP) request for the predicted demand address. The processor may also include units to arbitrate between generated IP pre-fetch requests and alternative pre-fetch requests.

Abstract: According to one embodiment of the invention, a method is disclosed for receiving a request for cacheable memory type data in a cache-controller in communication with a first cache memory; obtaining the requested data from a first memory device in communication with the first cache memory if the requested data does not resides in at least one of the cache-controller and the first cache memory; allocating a data storage buffer in the cache-controller for storage of the obtained data; and setting the allocated data storage buffer to a streaming data mode if the obtained data is a streaming data to prevent an unrestricted placement of the obtained streaming data into the first cache memory.

Abstract: Briefly, a method and apparatus of detecting and correcting soft error in a way of a ways group of a cache bank The detection of the soft error may be done by comparing between two replicas of the ways groups. The correction may be done by copying data from one replica of the ways group to another replica of the way group.

Abstract: In one embodiment, a buffer is presented. The buffer comprises a type designator to designate that the buffer is a streaming read buffer, and a plurality of use designators to indicate whether data within the buffer has been used. The data within the buffer is an uncacheable memory type, such as Uncacheable Speculative Write Combining (USWC) memory. Furthermore, in some embodiments, the buffer is allocated upon execution of a streaming read buffer instruction. In other embodiments, the data within the buffer can only be used once and cannot be cached elsewhere in the processor.

Abstract: A computer system having cache modules interconnected in series includes a first and a second cache module directly coupled to an address generating line for parallel lookup of data and data conversion logic coupled between the first cache module and said second cache module.

Abstract: A cache memory circuit is disclosed that includes a store hit buffer that buffers write operations to the cache memory circuit and that removes write operations from the critical speed path for the cache memory array. The store hit buffer includes circuitry for determining whether a read operation to the cache memory circuit is targeted for the write operation stored in the store hit buffer and circuitry for merging the write operation from the store hit buffer with the read operation.