Abstract: A nonvolatile memory cell having a floating gate for the storage of charges thereon has a control gate and a separate erase gate. The cell is programmed by hot channel electron injection and is erased by poly to poly Fowler-Nordheim tunneling. A method for making an array of unidirectional cells in a planar substrate, as well as an array of bidirectional cells in a substrate having a trench, is disclosed. An array of such cells and a method of making such an array is also disclosed.

Abstract: An integrated multilevel nonvolatile flash memory device has a memory array of a plurality of memory units arranged in a plurality of rows and columns. Each of the memory units has a plurality of memory cells with each memory cell for storing a multibit state. Each of the memory units stores encoded user data and overhead data. The partitioning of the encoded user data and the overhead data stored in a single memory unit may be done virtually. The result is a compact memory unit without the need for an index to overhead data for its associated user data.

Abstract: The present invention is a method and apparatus to program and/or to test a non-volatile memory cell to be programmed into a plurality of bit states (with each bit state having two states). More particularly, the method rapidly programs or tests such a cell by hard programming the cell when the cell is to be programmed into a state which permits the minimal amount of current t o flow in the channel. The charge pump integral with the memory device is capable of generating two types of pulses: a small incremental pulse, and a “hard” pulse, which is used only if the cell is to be programmed into the fully programmed state. For the states between fully programmed and fully erased, the incremental pulse is used to incrementally program the cell.

Abstract: An integrated multilevel nonvolatile flash memory device has a memory array of a plurality of memory units arranged in a plurality of rows and columns. Each of the memory units has a plurality of memory cells with each memory cell for storing a multibit state. Each of the memory units stores encoded user data and overhead data. The partitioning of the encoded user data and the overhead data stored in a single memory unit may be done virtually. The result is a compact memory unit without the need for an index to overhead data for its associated user data.

Abstract: The present invention is a method and apparatus to program and/or to test a non-volatile memory cell to be programmed into a plurality of bit states (with each bit state having two states). More particularly, the method rapidly programs or tests such a cell by hard programming the cell when the cell is to be programmed into a state which permits the minimal amount of current t o flow in the channel. The charge pump integral with the memory device is capable of generating two types of pulses: a small incremental pulse, and a “hard” pulse, which is used only if the cell is to be programmed into the fully programmed state. For the states between fully programmed and fully erased, the incremental pulse is used to incrementally program the cell.

Abstract: For negative gate erase and programming of non-volatile floating gate EEPROM devices, large positive or negative voltages from one single negative charge pump and from one single positive charge pump are selectively switched onto a one or more memory sectors of twin-well CMOS negative-gate-erase memory cells. The control gate is negative during erasing and positive during programming. In order for FLASH memories to have minimum layout area, small sectors or arrays of EEPROM cells can be erased all at once using a charge pump which includes two pump capacitors to provide negative voltages to the gate terminals of one or more series PMOS transistors.