Patents by Inventor Jack E. Murray
Jack E. Murray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11791252Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.Type: GrantFiled: June 1, 2022Date of Patent: October 17, 2023Inventors: Owen R. Fay, Jack E. Murray
-
Publication number: 20220293506Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.Type: ApplicationFiled: June 1, 2022Publication date: September 15, 2022Inventors: Owen R. Fay, Jack E. Murray
-
Publication number: 20220028771Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.Type: ApplicationFiled: October 4, 2021Publication date: January 27, 2022Inventors: Owen R. Fay, Jack E. Murray
-
Patent number: 11139229Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.Type: GrantFiled: August 9, 2019Date of Patent: October 5, 2021Assignee: Micron Technology, Inc.Inventors: Owen R. Fay, Jack E. Murray
-
Patent number: 10825762Abstract: Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.Type: GrantFiled: November 27, 2018Date of Patent: November 3, 2020Assignee: Micron Technology, Inc.Inventors: Brandon P. Wirz, Jack E. Murray
-
Patent number: 10825761Abstract: An electronic device includes a substrate, a structure over the substrate having an edge wall defining at least a portion of an opening exposing a surface of the substrate, and a dielectric material adjacent and in contact with the edge wall and an adjacent portion of the surface of the substrate. The dielectric material has a profile tapering downward from adjacent the edge wall toward the substrate. Other electronic devices include a substrate and a solder mask over the substrate. The solder mask defines an opening therethrough. A supplemental mask is within the opening of the solder mask, and has a sidewall that slopes away from the solder mask. A conductive structure is adjacent and in contact with at least one of the solder mask or the supplemental mask.Type: GrantFiled: November 27, 2018Date of Patent: November 3, 2020Assignee: Micron Technology, Inc.Inventors: Brandon P. Wirz, Jack E. Murray
-
Publication number: 20190363044Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.Type: ApplicationFiled: August 9, 2019Publication date: November 28, 2019Inventors: Owen R. Fay, Jack E. Murray
-
Patent number: 10381297Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.Type: GrantFiled: July 3, 2018Date of Patent: August 13, 2019Assignee: Micron Technology, Inc.Inventors: Owen R. Fay, Jack E. Murray
-
Patent number: 10276479Abstract: Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.Type: GrantFiled: October 11, 2017Date of Patent: April 30, 2019Assignee: Micron Technology, Inc.Inventors: Brandon P. Wirz, Jack E. Murray
-
Publication number: 20190109080Abstract: An electronic device includes a substrate, a structure over the substrate having an edge wall defining at least a portion of an opening exposing a surface of the substrate, and a dielectric material adjacent and in contact with the edge wall and an adjacent portion of the surface of the substrate. The dielectric material has a profile tapering downward from adjacent the edge wall toward the substrate. Other electronic devices include a substrate and a solder mask over the substrate. The solder mask defines an opening therethrough. A supplemental mask is within the opening of the solder mask, and has a sidewall that slopes away from the solder mask. A conductive structure is adjacent and in contact with at least one of the solder mask or the supplemental mask.Type: ApplicationFiled: November 27, 2018Publication date: April 11, 2019Inventors: Brandon P. Wirz, Jack E. Murray
-
Publication number: 20190109081Abstract: Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.Type: ApplicationFiled: November 27, 2018Publication date: April 11, 2019Inventors: Brandon P. Wirz, Jack E. Murray
-
Publication number: 20190109079Abstract: Methods of processing a semiconductor device include providing a patterned mask over a major surface of a substrate and comprising at least one opening exposing a conductive structure, and depositing particles of material by direct material deposition adjacent and in contact with an edge wall of the mask adjacent the at least one opening to form a supplemental mask over the major surface of the substrate. Other methods of processing semiconductor devices include depositing particles of material by direct material deposition adjacent a conductive structure at an intersection of the conductive structure and a surface of a substrate.Type: ApplicationFiled: October 11, 2017Publication date: April 11, 2019Inventors: Brandon P. Wirz, Jack E. Murray
-
Publication number: 20180315689Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.Type: ApplicationFiled: July 3, 2018Publication date: November 1, 2018Inventors: Owen R. Fay, Jack E. Murray
-
Patent number: 10032703Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.Type: GrantFiled: August 5, 2016Date of Patent: July 24, 2018Assignee: Micron Technology, Inc.Inventors: Owen R. Fay, Jack E. Murray
-
Publication number: 20160343690Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.Type: ApplicationFiled: August 5, 2016Publication date: November 24, 2016Inventors: Owen R. Fay, Jack E. Murray
-
Patent number: 9418926Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.Type: GrantFiled: May 18, 2015Date of Patent: August 16, 2016Assignee: Micron Technology, Inc.Inventors: Owen R. Fay, Jack E. Murray
-
Patent number: 6227076Abstract: Wrench structure for placement on over a generally circular workpiece in either a lateral or an axial direction and having a drive head with a cavity formed by a base member and an access cap, a bore formed thru the base member and cap around a rotational axis for accommodating the workpiece, a plurality of gripping jaws pivotally mounted within the cavity and arranged in a substantially circular pattern around the rotational axis and having gripping faces extending at least partially into the bore, each face being knurled and formed substantially on a radius line which makes an angle from about 6.0° to about 25° with a longitudinal axis of the jaw at a lateral midpoint of the face, and each face thereby having a neutral contact portion and a working contact portion.Type: GrantFiled: February 5, 2000Date of Patent: May 8, 2001Inventor: Jack E. Murray