Patents by Inventor Jack E. Shemer

Jack E. Shemer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4412285
    Abstract: A system using a sorting network to intercouple multiple processors so as to distribute priority messages to all processors is characterized by semaphore means accessible to both the local processors and the global resource via the network. Transaction numbers identifying tasks are employed in the messages, and interfaces at each processor are locally controlled to establish transaction number related indications of the current status of each task being undertaken at the associated processor. A single query to all processors via the network elicits a prioritized response that denotes the global status as to that task. The transaction numbers also are used as global commands and local controls for the flow of messages. A destination selection system based on words in the messages is used as the basis for local acceptance or rejection of messages. This arrangement together with the transaction number system provides great flexibility as to intercommunication and control.
    Type: Grant
    Filed: April 1, 1981
    Date of Patent: October 25, 1983
    Assignee: Teradata Corporation
    Inventors: Philip M. Neches, David H. Hartke, Richard C. Stockton, Martin C. Watson, David Cronshaw, Jack E. Shemer
  • Patent number: 4126894
    Abstract: A mapping arrangement for memory overlay wherein the address coordinates are referenced to a main serial memory. This main memory is partitioned into pages of equal size. An accelerator memory is concurrently loaded with a few pages representing a small portion of the main memory contents and is periodically overlayed with new memory contents on a page-at-a-time basis as the using system demands. During this overlay the fields of the accelerator memory are inscribed at corresponding main memory address coordinates together with code bits indicating whether certain memory fields go together and are therefore promoted as a single unit. The resulting effect is to cause an apparent increase in page size since more than one page is promoted as a consequence of a reference to a page not contained in the accelerator memory.
    Type: Grant
    Filed: February 17, 1977
    Date of Patent: November 21, 1978
    Assignee: Xerox Corporation
    Inventors: David Cronshaw, James R. Keddy, Jack E. Shemer, William D. Turner
  • Patent number: 4126893
    Abstract: A memory control processor adapted to expand a random access or accelerator memory by logical overlays which performs these overlays into memory fields (pages) on the basis of page usage history. To provide a quick reference to page use a chronological sequence is established by links rather than by reordering a stack. This link sequence is tied by very limited leads to the rest of the memory control processor and can therefore be updated during each memory access. In addition the memory control processor includes a task priority logic integrating various competing memory access requests with the overlay operations. To achieve the various transfer modes in the quickest time the memory control processor is organized around a wide control memory storing the task servicing sequences. The width of the control memory and the associated task logic allow general purpose microprogrammable direct memory access which may further be utilized in multiplexed fashion to accommodate various concurrent tasks.
    Type: Grant
    Filed: February 17, 1977
    Date of Patent: November 21, 1978
    Assignee: Xerox Corporation
    Inventors: David Cronshaw, William D. Turner, Jack E. Shemer
  • Patent number: 4110823
    Abstract: A distributed function processing system utilizing a conventional microprocessor operated as a text processor in combination with a plurality of other autonomous processing devices arranged to operate in a coherent processing system. One of the autonomous processors which is a memory control processor serves to periodically overlay a random access accelerator memory with the contents of a main memory system and concurrently resolves conflicts among various other autonomous memory service requests. This processor, therefore, accommodates the data rates of the main memory. The other processor is a display processor which generates signals to a video display system to provide a visual interface to the user and is therefore tied to the video rate. Accordingly, the processing burden is distributed within processors entailing differing rates operating autonomously.
    Type: Grant
    Filed: February 17, 1977
    Date of Patent: August 29, 1978
    Assignee: Xerox Corporation
    Inventors: David Cronshaw, Jack E. Shemer, William D. Turner, David Hartke, James R. Keddy, Wilbur E. DuVall, Warren M. Sterling
  • Patent number: 4080651
    Abstract: A memory control processor adapted to expand a random access or accelerator memory by logical overlays which performs these overlays into memory fields (pages) on the basis of page usage history. To provide a quick reference to page use a chronological sequence is established by links rather than by reordering a stack. This link sequence is tied by very limited leads to the rest of the memory control processor and can therefore be updated during each memory access. In addition the memory control processor includes a task priority logic integrating various competing memory access requests with the overlay operations. To achieve the various transfer modes in the quickest time the memory control processor is organized around a wide control memory storing the task servicing sequences. The width of the control memory and the associated task logic allow general purpose microprogrammable direct memory access which may further be utilized in multiplexed fashion to accommodate various concurrent tasks.
    Type: Grant
    Filed: February 17, 1977
    Date of Patent: March 21, 1978
    Assignee: Xerox Corporation
    Inventors: David Cronshaw, William D. Turner, Jack E. Shemer
  • Patent number: 4080652
    Abstract: A memory control processor adapted to expand a random access or accelerator memory by logical overlays which performs these overlays into memory fields (pages) on the basis of page usage history. To provide a quick reference to page use a chronological sequence is established by links rather than by reordering a stack. This link sequence is tied by very limited leads to the rest of the memory control processor and can therefore be updated during each memory access. In addition the memory control processor includes a task priority logic integrating various competing memory access requests with the overlay operations. To achieve the various transfer modes in the quickest time the memory control processor is organized around a wide control memory storing the tank servicing sequences. The width of the control memory and the associated task logic allow general purpose microprogrammable direct memory access which may further be utilized in multiplexed fashion to accommodate various concurrent tasks.
    Type: Grant
    Filed: February 17, 1977
    Date of Patent: March 21, 1978
    Assignee: Xerox Corporation
    Inventors: David Cronshaw, William D. Turner, Jack E. Shemer