Patents by Inventor Jack E. Weimer

Jack E. Weimer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11067629
    Abstract: Aspects of the present application are directed to an automated test equipment (ATE) and methods for operating the same for testing high-power electronic components. The inventor has recognized and appreciated an ATE that provides both high-power alternating-current (AC) and direct-current (DC) testing in a single test system can lead to high throughput testing for high-power components with reduced system hardware complexity and cost. Aspects of the present application provide a synchronized inductor switch module and both a high-precision digitizer and a high-speed digitizer for capturing DC and AC characteristics of a high-power transistor.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 20, 2021
    Assignee: Teradyne, Inc.
    Inventor: Jack E. Weimer
  • Patent number: 11041900
    Abstract: A test system and test techniques for accurate high-current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: June 22, 2021
    Assignee: Teradyne, Inc.
    Inventor: Jack E. Weimer
  • Publication number: 20200379043
    Abstract: Aspects of the present application are directed to an automated test equipment (ATE) and methods for operating the same for testing high-power electronic components. The inventor has recognized and appreciated an ATE that provides both high-power alternating-current (AC) and direct-current (DC) testing in a single test system can lead to high throughput testing for high-power components with reduced system hardware complexity and cost. Aspects of the present application provide a synchronized inductor switch module and both a high-precision digitizer and a high-speed digitizer for capturing DC and AC characteristics of a high-power transistor.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 3, 2020
    Applicant: Teradyne, Inc.
    Inventor: Jack E. Weimer
  • Patent number: 10698020
    Abstract: A test system and test techniques for accurate high current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: June 30, 2020
    Assignee: Teradyne, Inc.
    Inventor: Jack E. Weimer
  • Patent number: 9989584
    Abstract: Example automatic test equipment (ATE) may include: a device interface board (DIB) on which the DUT is mounted; a system for sending signals to, and receiving signals from, the DUT; and an energy source unit (ESU) to provide current to the DUT via the DIB, where the ESU includes current paths to provide the current, and where the current paths are configured to limit a combined inductance of the current paths.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: June 5, 2018
    Assignee: Teradyne, Inc.
    Inventors: Jack E. Weimer, Steven C. Price, David R. Hanna, Jeffry Baenen, Scott Skibinski
  • Publication number: 20160011256
    Abstract: Example automatic test equipment (ATE) may include: a device interface board (DIB) on which the DUT is mounted; a system for sending signals to, and receiving signals from, the DUT; and an energy source unit (ESU) to provide current to the DUT via the DIB, where the ESU includes current paths to provide the current, and where the current paths are configured to limit a combined inductance of the current paths.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 14, 2016
    Inventors: Jack E. Weimer, Steven C. Price, David R. Hanna, Jeffry Baenen, Scott Skibinski
  • Publication number: 20150276803
    Abstract: A test system and test techniques for accurate high-current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 1, 2015
    Applicant: Teradyne, Inc.
    Inventor: Jack E. Weimer
  • Publication number: 20150276799
    Abstract: A test system and test techniques for accurate high current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 1, 2015
    Applicant: Teradyne, Inc.
    Inventor: Jack E. Weimer