Patents by Inventor Jack FULLER

Jack FULLER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12530306
    Abstract: In an example there is provided a configurable integrated circuit. The configurable integrated circuit comprises a configuration pin, configuration circuitry, and a controller. The configuration pin is for coupling with an external memory device. The configuration circuitry is to determine a resistance value between the configuration pin and a reference voltage. The controller configured to select a configuration mode for the integrated circuit based on the resistance value determined by the configuration circuitry. The configuration mode is one of an internal configuration mode in which the integrated circuit is configured based on data stored in the integrated circuit, and an external configuration mode in which the integrated circuit is configured based on data read from an external memory device coupled to the configuration pin.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: January 20, 2026
    Assignee: Cirrus Logic Inc.
    Inventor: Jack Fuller
  • Publication number: 20250233771
    Abstract: A system for transmission of primary and secondary data, the system comprising: a bus; a parent node coupled to the bus; and a plurality of child nodes, each coupled to the bus, wherein: the parent node is configured to periodically transmit a time domain multiplexing (TDM) cycle beacon to the bus, wherein the TDM cycle beacon signals a start of a primary data transmission interval, and wherein the primary data transmission interval is a period reserved for transmission of primary data by the parent node and the plurality of child nodes; the parent node and each of the plurality of child nodes are operable to, responsive to the TDM cycle beacon, transmit primary data for a current TDM beacon period associated with the TDM cycle beacon to the bus during the primary data transmission interval; and the parent node and the plurality of child nodes are operable to transmit secondary data to the bus during a secondary data transmission interval between an end of the primary transmission interval and transmission by
    Type: Application
    Filed: January 8, 2025
    Publication date: July 17, 2025
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Michael CHANDLER-PAGE, Jack FULLER, Amr ELSLEHDAR
  • Publication number: 20240354266
    Abstract: In an example there is provided a configurable integrated circuit. The configurable integrated circuit comprises a configuration pin, configuration circuitry, and a controller. The configuration pin is for coupling with an external memory device. The configuration circuitry is to determine a resistance value between the configuration pin and a reference voltage. The controller configured to select a configuration mode for the integrated circuit based on the resistance value determined by the configuration circuitry. The configuration mode is one of an internal configuration mode in which the integrated circuit is configured based on data stored in the integrated circuit, and an external configuration mode in which the integrated circuit is configured based on data read from an external memory device coupled to the configuration pin.
    Type: Application
    Filed: April 24, 2023
    Publication date: October 24, 2024
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventor: Jack FULLER
  • Patent number: 11668738
    Abstract: Circuitry for detecting a capacitive load coupled between a first node and a second node, the circuitry comprising: drive circuitry for applying a first voltage to a first node over a first time period; processing circuitry configured to: measure a second voltage at the first node; and determine that the load is a capacitive load based on the second voltage.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: June 6, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Mehul Mistry, Rupesh Khare, Jack Fuller
  • Publication number: 20220404407
    Abstract: Circuitry for detecting a capacitive load coupled between a first node and a second node, the circuitry comprising: drive circuitry for applying a first voltage to a first node over a first time period; processing circuitry configured to: measure a second voltage at the first node; and determine that the load is a capacitive load based on the second voltage.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 22, 2022
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Mehul MISTRY, Rupesh KHARE, Jack FULLER