Abstract: Power management for a multi-processor chip includes a centralized global power manager that monitors global power for the whole chip, and local power managers. Local power managers manage power for local blocks such as processor cores, caches, and memory controllers. When a local block executes an instruction or accesses memory, an event is generated and looked up in a local power estimate table. A local power estimate for that event is sent to the global power manager, which sums all local power estimates received from all local blocks. An exponential moving average (EMA) is generated and compared to a global power threshold. When global power is over the threshold, local targets are sent to power managers that generate and monitor local power averages that must remain under the local target. The local block is throttled by the local power manager to reduce power when the local target is exceeded.

Abstract: Several cluster chips and a shared main memory are connected by interconnect buses. Each cluster chip has multiple processors using multiple level-2 local caches, two memory controllers and two snoop tag partitions. The interconnect buses connect all local caches to all snoop tag partitions on all cluster chips. Each snoop tag partition has all the system's snoop tags for a partition of the main memory space. The snoop index is a subset of the cache index, with remaining chip-select and interleave address bits selecting which of the snoop tag partitions on the multiple cluster chips stores snoop tags for that address. The number of snoop entries in a snoop set is equal to a total number of cache entries in one cache index for all local caches on all cluster chips. Cache coherency request processing is distributed among the snoop tag partitions on different cluster chips, reducing bottlenecks.

Abstract: A load/store centric exception handling system provided in accordance with the principles of this invention that provides a more efficient processor exception handling system wherein a speculative commit control signal (SpecComId) is generated whenever a load or store instructions is detected by the pipeline issuing unit (PIU). This speculative commit signal is sent to a Load Store Unit (LSU) which combines the SpecComID with the completed instructions in its pipeline to generate an actual commit signal (ComId) that is coupled to other processor units. Depending on what type of instructions are in the pipeline, SpecComID can be generated as early as Q stage or as late as C stage. LSU or Exc Free instructions can be speculatively committed in Q stage to move the speculative commit point up in processor pipeline. Exc Taking instructions speculatively commit in the C stage to move the speculative commit point down pipeline.

Abstract: A method and an apparatus for implementing mixed scalar and vector values in a digital processing system. In one embodiment, a digital processing system, which contains processing unit and memories, is capable of identifying a first data in a first scalar register and a second data in a vector register. Upon fetching the first data as a first operand and the second data as a second operand, the processing unit performs an operation between the first and second operands in response to an operator. After operations, the result is subsequently stored in a second scalar register.

Abstract: A method and a device including, in one embodiment, a multiply array and at least one adder to perform a floating-point multiplication followed by an addition when operands are in floating-point format. The device is also configured to perform an integer multiplication followed by an accumulation when operands are in integer format. The device is further configured to perform a floating-point multiply-add or an integer multiply-accumulation in response to control signals. In another embodiment, the device contains an adder and the adder is capable of performing a floating-point addition and an integer accumulation. The adder is configured to be extra wide to reduce operand misalignment. Moreover, the device stalls the process in response to operand misalignment.

Abstract: A dual access debugging architecture. This architecture allows the microprocessor to select between external debugging, supported via the physical system interface, and internal debugging, supported via logic within the microprocessor which is controlled by decoded software instructions. In one example of the present invention, a microprocessor includes a system bus interface and a program decoder which is coupled to the system bus interface. The system bus interface is coupled to a system bus to which external memory is coupled. Debugging operations are stored as debugging instructions in the external memory. When these debugging instructions are retrieved from memory, through the system bus and the system bus interface, they are decoded in the program decoder of the microprocessor and they in turn cause the microprocessor to enter a first debugging mode which is controlled by the debugging instructions. The first debugging mode may be referred to as an internal programmable method.

Abstract: One embodiment of the present invention provides a state machine that receives as input a clock signal and determines a frequency relationship between circuits. The state machine generates outputs that control buffer circuits. The buffer circuits latch signals input to them until the output signals from the state machine cause the buffer circuits to latch new input signals. The buffer circuits are used to latch data until that data can be used appropriately.

Abstract: A method and an apparatus for data processing between multiple execution units using local and global register bypasses is disclosed. In one embodiment, the device contains a register file, at least two bypass circuits, a plurality of execution units, and a control circuit. Each bypass circuit connects to at least one execution unit. The control circuit, which is coupled to the execution units, limits no more than one clock delay per each execution clock cycle. The control circuit further designates delay clock cycles for handling delays.

Abstract: A method and an apparatus using, in one embodiment, a multiple split mode for issuing multiple read or write requests that may be used during a data transaction within a computer system. In one embodiment, a processing unit comprises a bus arbitrator having bus control lines for controlling a bus, which transmits address and data information. The arbitrator is capable of issuing multiple consecutive read or write requests including at least one read request on the bus without releasing control by the processing unit over the bus during the consecutive read or write requests. In addition, the arbitrator is also designed to abort consecutive read requests during address cycles in response to bus control lines.