Abstract: A buffered crosspoint matrix (20) of an asynchronous transfer mode switch (10) includes a plurality of switching elements (38) for receiving and switching segments containing asynchronous transfer mode cells. Each switching element (38) receives segments at a plurality of multicast/routing elements (52). Each multicast/routing element generates insert enable signals for each segment to route segments to selected crosspoints (58) of a plurality of vertical bar elements (54). Each vertical bar element (54) includes a plurality of queuing systems (90) for receiving and storing segments within an associated common buffer area (94). Segments are prioritized according to class of service and segment locations within the common buffer area (94) are stored in subqueues (104) according to their corresponding class of service. Each queuing system (90) performs a first phase contention resolution tournament to determine an oldest segment of those segments at the head of the subqueue (104) list.

Abstract: A buffered crosspoint matrix (20) of an asynchronous transfer mode switch (10) includes a plurality of switching elements (38) for receiving and switching segments containing asynchronous transfer mode cells. Each switching element (38) receives segments at a plurality of multicast/routing elements (52). Each multicast/routing element generates insert enable signals for each segment to route segments to selected crosspoints (58) of a plurality of vertical bar elements (54). Each vertical bar element (54) includes a plurality of queuing systems (90) for receiving and storing segments within an associated common buffer area (94). Segments are prioritized according to class of service and segment locations within the common buffer area (94) are stored in subqueues (104) according to their corresponding class of service. Each queuing system (90) performs a first phase contention resolution tournament to determine an oldest segment of those segments at the head of the subqueue (104) list.

Abstract: A method and apparatus for a high speed asynchronous transfer mode switch is provided which includes an input buffer circuit coupled to communication lines for receiving and temporarily storing packets from the communication lines, a switch comprising one or more planes and output circuitry for coupling the switch outputs to respective communication lines. The switch is comprised of a plurality of switching elements, each of which include a sorter for ranking packets responsive to addresses associated with the packets, compare circuitry for receiving the ranked packets from the sorter and passing up to a predetermined number of packets having the same address, and routing circuitry for routing the packets passed by the compare circuitry responsive to the associated addresses. After a packet is successfully transferred through the switch, an acknowledge signal is returned to the sending input buffer circuit.

Abstract: A switching system (10) configured in a ring topology (14) is disclosed. The system (10) causes one or more 125 microsecond isochronous frames (20) to circulate in the ring (14) at any given instant in time. A delay circuit (22) temporarily saves an oldest one of the isochronous frames (20) until a youngest one of the isochronous frames (20) has completed its transmission. Consequently, an integral number of isochronous frames (20) circulate in ring (14). The isochronous frame (20) is partitioned to support a random access tunnel channel (26) and a plurality of independently controlled cells (28), which provide a variety of deterministic access services. Each cell (28) contains a control field (30) that contains sufficient information to specify the type of switching service provided by the cell (28) and various service parameters. A time multiplexer (42) separates the tunnel channel (26) from the cells (28).