Abstract: A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter based on the relative speed. In one embodiment, an integrated circuit may include a ring oscillator, a shift register having a clock input coupled to an output of the ring oscillator, and compare logic coupled to an output of the shift register. The shift register is enabled in response to initiating a memory access to a memory and disabled in response to completing the memory access. The compare logic provides a relative speed indicator representative of a relative speed of the memory.

Abstract: An electronic device includes a memory cell that utilizes a bi-directional low impedance, low voltage drop full pass gate to connect a bit cell to a bit write line during a write phase, and during a read phase the full pass gate can remain off and a high input impedance read port can acquire and transmit the logic state stored by the memory cell to another subsystem. The full pass gate can be implemented by connecting a P type metal semiconductor field effect transistor (PMOS) in parallel with an NMOS device and driving the gates of the transistors with a differential signal. When a write operation requires a current to flow in a first direction, the PMOS device provides a negligible voltage drop, and when the write operation requires current to flow in a second or the opposite direction, the NMOS device can provide a negligible voltage.

Abstract: A monolithic semiconductor body (26) resides in an opening (16) formed in an insulating layer (14). The monolithic semiconductor body (26) includes an elongated region (20) filling the opening (16) in the insulating layer (14) and contacting a semiconductor region (12). The monolithic semiconductor body (26) further includes a surface region (24) overlying the elongated region (20) and a portion of the surface (22) of the insulating layer (14) adjacent to the opening (16). The monolithic semiconductor body (26) is fabricated by first depositing a layer of semiconductor material into the opening (16), then planarizing the surface of the insulating layer (14). Next, a selective deposition process is carried out to form the surface region (24) using the semiconductor material in the opening (16) as a nucleation site. The radius of curvature of the surface region (24) is determined by the amount of controlled overgrowth during the selective deposition process.

Abstract: An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define a segmented channel region (16) therebetween. A select gate electrode (18) overlies a first channel region (24) and separates the floating gate electrode (2) from the source region (12). The control gate electrode (20) overlies a third channeI region (28) and separates the floating gate electrode (22) from the drain region (14). The floating gate electrode (22) overlies a second channel region (26) and is separated therefrom by a thin tunnel oxide layer (42). The EEPROM device of the invention can be programmed by either source side injection, or by Fowler-Nordheim tunneling. Additionally, a process is provided for the fabrication of an EEPROM array utilizing adjacent select gate electrodes (18, 18') as a doping mask.

Abstract: An EEPROM memory array includes a plurality of memory cells having a floating gate electrode (22) formed as a sidewall spacer adjacent to a control gate electrode (20). Source and drain regions (12, 14) reside in a semiconductor substrate (10) and define a segmented channel region (16) therebetween. A select gate electrode (18) overlies a first channel region (24) and separates the floating gate electrode (22) from the source region (12). The control gate electrode (20) overlies a third channel region (28) and separates the floating gate electrode (22) from the drain region (14). The floating gate electrode (22) overlies a second channel region (26) and is separated therefrom by a thin tunnel oxide layer (42). The EEPROM device of the invention can be programmed by either source side injection, or by Fowler-Nordheim tunneling. Additionally, a process is provided for the fabrication of an EEPROM array utilizing adjacent select gate electrodes (18, 18') as a doping mask.