Patents by Inventor Jack K. Keller

Jack K. Keller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Tri-state logic buffer circuit
    Patent number: 4417162
    Abstract: A first MOS (metal-oxide-semiconductor) NOR-gate device feeding a second MOS NOR-gate device feeding an MOS output load device is arranged to yield a three output level buffer circuit, that is, whose output to a common data bus line can be "high" ("1"), "low" ("0"), or of very high impedance ("floating"). Each NOR-gate contains a low .beta. ("load") depletion mode type of MOS transistor and a high .beta. ("driver") enhancement mode type of MOS; the output load device contains an output driver enhancement mode type of MOS transistor and an output load MOS transistor having a threshold intermediate that of the depletion mode and enhancement mode type of MOS transistor. In this manner, only a single voltage source V.sub.DD, or typically about +5 volts in N-MOS integrated circuit technology is required to power the buffer circuit completely.
    Type: Grant
    Filed: September 9, 1981
    Date of Patent: November 22, 1983
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Jack K. Keller, Gilbert L. Mowery, Jr.