Abstract: A computer-implemented transaction processing system includes a card reader and a plurality of modules each comprising code that executes in the processor. The card reader transfers credit card data from a credit card of a customer to a memory of the computer. A check presentation module is operative to calculate a sales tax associated with a price of a product sold to the customer. An approval module is operative to obtain an approval against the credit card data in the memory for at least the price of the product and the sales tax and thereby define an approved sale transaction. A revenue settlement module and a tax settlement module are operative to settle respective portions of the sales transaction(s) to different accounts, such that a revenue portion goes to a first account free of any sales tax, and a sales tax portion goes to the other account.

Abstract: A computer-implemented transaction processing system includes a card reader and a plurality of modules each comprising code that executes in the processor. The card reader transfers credit card data from a credit card of a customer to a memory of the computer. A check presentation module is operative to calculate a sales tax associated with a price of a product sold to the customer. An approval module is operative to obtain an approval against the credit card data in the memory for at least the price of the product and the sales tax and thereby define an approved sale transaction. A revenue settlement module and a tax settlement module are operative to settle respective portions of the sales transaction(s) to different accounts, such that a revenue portion goes to a first account free of any sales tax, and a sales tax portion goes to the other account.

Abstract: A low power high sensitivity detector having two pairs of MOS cross coupled transistors, voltage equalization circuitry, and a single input, with no external reference, forms the basic configuration of a detector-level shifter circuit which is compatible with today's single chip large capacity memories. The lengths of the channels of one of the pairs of cross coupled transistors are designed to be longer than the other pair. This provides a built-in imbalance which provides good tolerance to transistor parameter variation due to semiconductor processing variations.

Abstract: A logic gate circuit includes a resistance divider input to the base of an input transistor and a multiple emitter output transistor in an emitter follower configuration. The circuit has favorable switching speed and power dissipation characteristics and reduces the effect of both capacitive loading and series resistance in signal interconnections. An efficient layout of one such logic circuit has intercell wiring channels formed across the circuit and has the inputs and outputs of the circuit arranged in two lines each of which crosses perpendicular to the wiring channels.