Abstract: A hierarchical modular arbitration architecture for a mobile platform guidance system is disclosed. In embodiments, the architecture comprises a hierarchy of arbitration layers, each arbitration layer narrower in scope than the layer above (e.g., mission objective arbitrators, route arbitrators, path arbitrators). Each arbitration layer includes one or more objective-based arbitrators in communication with one or more applications or modes. Each arbitrator receives control input (e.g., from the pilot, from aircraft sensors) and control signals from the level above, selecting a mode to make active based on decision agents within the arbitrator layer which control mode priorities and sequencing (e.g., some flight objectives may involve multiple arbitrators and their subject applications coordinating in sequence).

Abstract: An interface device to provide a data and address path between a data processor, a memory and peripheral devices. The interface device includes an internal arithmetic and logic unit to provide a means for generating and/or modifying addresses for the memory or peripheral devices. The device further includes a plurality of registers for temporarily storing data or addresses as well as information associated with addressing functions, for example, program counter, index register, stack pointer and page addresses. The interface device may be used singly or in combination with like devices as in a slice processing system.

Abstract: An adder provides either binary or binary coded decimal operation under the selection of a control input. The data inputs are a pair of four bit operands and a carry in for providing an additional capability of greater than four bits. Outputs, in addition to the four bit result, include carry propagate and carry generate signals for the four bit group. Binary operation is conventional. For binary coded decimal operation, the adder corrects an initial binary result to the binary coded decimal format by adding six when there is a group carry generate signal present thus forming an intermediate result. This intermediate result is formed before the occurrence of the carry in from a preceding stage. In the final stage of the adder, the intermediate result is incremented to form the final four bit result if there is a carry in.

Abstract: A dual function capability is incorporated into one input of an emitter coupled logic gate to allow a user to selectively enable the logic circuit to operate in a multifunction mode. The dual function input can recognize both normal binary voltage levels and operate as a conventional input for digital information, and also recognize voltage levels not within the normal binary voltage levels and modify the circuit function correspondingly.