Patents by Inventor Jack L. Glenn

Jack L. Glenn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7279773
    Abstract: A protection device for handling energy transients includes a plurality of basic unit Zener diodes connected in series to achieve a desired breakdown voltage. Each of the basic unit Zener diodes is formed in a first-type substrate. Each of the basic unit Zener diodes comprises a second-type well formed in the substrate, a second-type Zener region formed in the second-type well and a first-type+ region formed over the second-type Zener region between a first and second second-type+ region.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: October 9, 2007
    Assignee: Delphi Technologies, Inc.
    Inventors: Jack L. Glenn, Troy D. Clear, Mark W. Gose, John M. Dikeman
  • Patent number: 6762453
    Abstract: A programmable memory transistor (PMT) comprising an IGFET and a coupling capacitor in a semiconductor substrate. The IGFET comprises source and drain regions, a channel therebetween, a gate insulator overlying the channel, and a first floating gate over the gate insulator. The capacitor comprises a lightly-doped well of a first conductivity type, heavily-doped contact and injecting diffusions of opposite conductivity types in the lightly-doped well, a control gate insulator overlying a surface region of the lightly-doped well between the contact and injecting diffusions, a second floating gate on the control gate insulator, and a conductor contacting the lightly-doped well through the contact and injecting diffusions. The first and second floating gates are preferably patterned from a single polysilicon layer, such that the second floating gate is capacitively coupled to the lightly-doped well, and the latter defines a control gate for the first floating gate.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: July 13, 2004
    Assignee: Delphi Technologies, Inc.
    Inventors: Thomas K. Simacek, Thomas W. Kotowski, Jack L. Glenn, Alireza F. Borzabadi
  • Publication number: 20040119113
    Abstract: A programmable memory transistor (PMT) comprising an IGFET and a coupling capacitor in a semiconductor substrate. The IGFET comprises source and drain regions, a channel therebetween, a gate insulator overlying the channel, and a first floating gate over the gate insulator. The capacitor comprises a lightly-doped well of a first conductivity type, heavily-doped contact and injecting diffusions of opposite conductivity types in the lightly-doped well, a control gate insulator overlying a surface region of the lightly-doped well between the contact and injecting diffusions, a second floating gate on the control gate insulator, and a conductor contacting the lightly-doped well through the contact and injecting diffusions. The first and second floating gates are preferably patterned from a single polysilicon layer, such that the second floating gate is capacitively coupled to the lightly-doped well, and the latter defines a control gate for the first floating gate.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Inventors: Thomas K. Simacek, Thomas W. Kotowski, Jack L. Glenn, Alireza F. Borzabadi
  • Patent number: 5134454
    Abstract: An integrated circuit vertical bipolar transistor includes monocrystalline emitter, base and collector contacts for electrically contacting the transistor's emitter, base and collector regions, respectively. The collector, base contact and emitter contact are preferably insulated from one another by oxide regions which are formed from the monocrystalline collector and monocrystalline base contacts. Since all of the contacts are formed of monocrystalline material and the oxide isolation is formed from monocrystalline material, high performance devices are formed. The process of forming the transistor self aligns the base to the collector and the emitter to the base. The monocrystalline base contact is also self aligned to the base and the monocrystalline emitter contact is self aligned to the emitter. The process preferably uses epitaxial lateral overgrowth and selective epitaxial growth from a mesa region to form the monocrystalline contacts.
    Type: Grant
    Filed: June 27, 1991
    Date of Patent: July 28, 1992
    Assignee: Purdue Research Foundation
    Inventors: Gerold W. Neudeck, Jack L. Glenn, Jr.
  • Patent number: 5118634
    Abstract: An integrated circuit vertical bipolar transistor includes monocrystalline emitter, base and collector contacts for electrically contacting the transistor's emitter, base and collector regions, respectively. The collector, base contact and emitter contact are preferably insulated from one another by oxide regions which are formed from the monocrystalline collector and monocrystalline base contacts. Since all of the contacts are formed of monocrystalline material and the oxide isolation is formed from monocrystalline material, high performance devices are formed.The process of forming the transistor self aligns the base to the collector and the emitter to the base. The monocrystalline base contact is also self aligned to the base and the monocrystalline emitter contact is self aligned to the emitter. The process preferably uses epitaxial lateral overgrowth and selective epitaxial growth from a mesa region to form the monocrystalline contacts.
    Type: Grant
    Filed: September 26, 1990
    Date of Patent: June 2, 1992
    Assignee: Purdue Research Foundation
    Inventors: Gerold W. Neudeck, Jack L. Glenn, Jr.