Abstract: A package for mounting, interconnecting, and cooling a large number of integrated circuit semiconductor devices having a sintered multilayer ceramic substrate provided with an internal metallurgy network made up of voltage planes, X and Y signal planes, and fan-out planes, with I/O pins on the bottom surface, and a plurality of asymmetrical solder pad clusters for flip chip bonding to a plurality of integrated circuit devices on the top surface, a plurality of integrated circuit devices bonded to the solder pad clusters, at least one row elongated engineering change pads surrounding each pad cluster, each pad provided with a severable surface link, the I/O pins connected to the internal network of the substrate and arranged in clusters with the powering voltages of each device located directly beneath the device thereby minimizing voltage drop, and signal voltages inputted through the I/O pins interspersed between the clusters of power pins, a cap for forming an enclosure over at least the top surface of the