Patents by Inventor Jack Lavier
Jack Lavier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11593138Abstract: A physical server with an offload card including a SoC (system-on-chip) and a FPGA (field programmable gate array) is disclosed. According to one set of embodiments, the SoC can be configured to offload one or more hypervisor functions from a CPU complex of the server that are suited for execution in software, and the FPGA can be configured to offload one or more hypervisor functions from the CPU complex that are suited for execution in hardware.Type: GrantFiled: March 3, 2020Date of Patent: February 28, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Derek Chiou, Andrew Putnam, Daniel Firestone, Jack Lavier
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Publication number: 20200371828Abstract: A physical server with an offload card including a SoC (system-on-chip) and a FPGA (field programmable gate array) is disclosed. According to one set of embodiments, the SoC can be configured to offload one or more hypervisor functions from a CPU complex of the server that are suited for execution in software, and the FPGA can be configured to offload one or more hypervisor functions from the CPU complex that are suited for execution in hardware.Type: ApplicationFiled: March 3, 2020Publication date: November 26, 2020Inventors: Derek CHIOU, Andrew PUTNAM, Daniel FIRESTONE, Jack LAVIER
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Patent number: 9013200Abstract: Electronic circuits and methods are provided for use in hot-swappable circuit board applications. Circuitry detects an electrical ground connection and signals operation of a hot-swap controller. Detection of stable operating power causes a hierarchical startup of plural voltage regulators. Sensing stable output power from the last of the voltage regulators triggers the configuration of one or more programmable devices. Circuitry and other resources of a hot-swappable circuit board are protected against electrical transient-related damage by virtue of the present teachings.Type: GrantFiled: December 4, 2009Date of Patent: April 21, 2015Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ray Woodward, Samuel M. Babb, Kelly Pracht, Jack Lavier
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Patent number: 8870325Abstract: In an embodiment, a method of compensating for capacitance change in a piezoelectric element of a fluid ejection device includes sensing a current driving a piezoelectric element, determining from the current that capacitance of the piezoelectric element has changed, and altering a rise time of the current driving the piezoelectric element to compensate for the changed capacitance.Type: GrantFiled: April 28, 2011Date of Patent: October 28, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Peter Mardilovich, Jack Lavier
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Publication number: 20130321507Abstract: In an embodiment, a method of compensating for capacitance change in a piezoelectric element of a fluid ejection device includes sensing a current driving a piezoelectric element, determining from the current that capacitance of the piezoelectric element has changed, and altering a rise time of the current driving the piezoelectric element to compensate for the changed capacitance.Type: ApplicationFiled: April 28, 2011Publication date: December 5, 2013Inventors: Peter Mardilovich, Jack Lavier
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Publication number: 20120119775Abstract: Electronic circuits and methods are provided for use in hot-swappable circuit board applications. Circuitry detects an electrical ground connection and signals operation of a hot-swap controller. Detection of stable operating power causes a hierarchical startup of plural voltage regulators. Sensing stable output power from the last of the voltage regulators triggers the configuration of one or more programmable devices. Circuitry and other resources of a hot-swappable circuit board are protected against electrical transient-related damage by virtue of the present teachings.Type: ApplicationFiled: December 4, 2009Publication date: May 17, 2012Inventors: Ray Woodward, Samuel M. Babb, Kelly Pracht, Jack Lavier
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Patent number: 7692910Abstract: A control logic detects voltage regulator failure in a power supply. The control logic comprises first and second lines configured for respective connection to a controller node and a phase node of a voltage regulator, a delay element coupled to the first line configured to delay signals at the controller node into alignment with signals at the phase node, and a level detector coupled to the second line configured to convert the signals at the phase node into at least two digital representations indicative of respective signal thresholds. A logic compares timing of the delayed signals with the digital representations and detects occurrence of a voltage regulator fault based on the timing comparison.Type: GrantFiled: March 29, 2007Date of Patent: April 6, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jack Lavier, Samuel M. Babb, Kelly Jean Pracht
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Patent number: 7449912Abstract: Power supplies are disclosed herein. One embodiment of a power supply comprises a first input and a second input, wherein the first input and the second input are connectable to a pulse width modulation controller and wherein a pulse width modulation signal is outputable from the pulse width modulation controller. A power stage connected to the first input and the second input. A first comparator having a first comparator first input is connected to the first input and a first comparator second input connected to the output of the power stage. A change of voltage at the output of the first comparator constitutes a difference in phase between the first input and the output of the power stage.Type: GrantFiled: January 26, 2007Date of Patent: November 11, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kelly Jean Pracht, Samuel M. Babb, Jack Lavier
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Patent number: 7443055Abstract: Systems and methods for providing redundant voltage regulation are provided. A representative method incorporates: providing a first voltage regulator and a second voltage regulator, the second voltage regulator having output rectifiers; electrically connecting the first voltage regulator to a load such that the first voltage regulator independently powers the load; disabling the output rectifiers of the second voltage regulator; detecting a fault of the first voltage regulator; responsive to the fault, enabling the output rectifiers of the second voltage regulator such that the second voltage regulator independently powers the load.Type: GrantFiled: October 24, 2006Date of Patent: October 28, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kelly Jean Pracht, Jack Lavier, Samuel M. Babb
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Publication number: 20080239593Abstract: A control logic detects voltage regulator failure in a power supply. The control logic comprises first and second lines configured for respective connection to a controller node and a phase node of a voltage regulator, a delay element coupled to the first line configured to delay signals at the controller node into alignment with signals at the phase node, and a level detector coupled to the second line configured to convert the signals at the phase node into at least two digital representations indicative of respective signal thresholds. A logic compares timing of the delayed signals with the digital representations and detects occurrence of a voltage regulator fault based on the timing comparison.Type: ApplicationFiled: March 29, 2007Publication date: October 2, 2008Inventors: Jack Lavier, Samuel M. Babb, Kelly Jean Pracht
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Publication number: 20080180108Abstract: Power supplies are disclosed herein. One embodiment of a power supply comprises a first input and a second input, wherein the first input and the second input are connectable to a pulse width modulation controller and wherein a pulse width modulation signal is outputable from the pulse width modulation controller. A power stage connected to the first input and the second input. A first comparator having a first comparator first input is connected to the first input and a first comparator second input connected to the output of the power stage. A change of voltage at the output of the first comparator constitutes a difference in phase between the first input and the output of the power stage.Type: ApplicationFiled: January 26, 2007Publication date: July 31, 2008Inventors: Kelly Jean Pracht, Samuel M. Babb, Jack Lavier
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Publication number: 20080093933Abstract: Systems and methods for providing redundant voltage regulation are provided. A representative method incorporates: providing a first voltage regulator and a second voltage regulator, the second voltage regulator having output rectifiers; electrically connecting the first voltage regulator to a load such that the first voltage regulator independently powers the load; disabling the output rectifiers of the second voltage regulator; detecting a fault of the first voltage regulator; responsive to the fault, enabling the output rectifiers of the second voltage regulator such that the second voltage regulator independently powers the load.Type: ApplicationFiled: October 24, 2006Publication date: April 24, 2008Inventors: Kelly Jean Pracht, Jack Lavier, Samuel M. Babb