Patents by Inventor Jack M. Higman
Jack M. Higman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10964362Abstract: Disclosed is a three-port static random access memory (3P-SRAM) that performs XNOR operations. The cell has a write port and first and second read ports. Read operations are enabled through either the first read port using a first read wordline and a common read bitline or the second read port using a second read wordline and the common read bitline. Read wordline activation is controlled such that only one read wordline is activated (i.e., receives a read pulse) at a time. As a result, a read operation through either read port effectively accomplishes an XNOR operation. Also disclosed is a memory array, which incorporates such cells and which performs XNOR-bitcount-compare functions. Since XNOR-bitcount-compare functions are used in XNOR-NET type binary neural networks (BNNs), the memory array can be employed for implementing such a BNN designed for improved performance, scalability, and manufacturability. Also disclosed is an in-memory computing method.Type: GrantFiled: April 25, 2019Date of Patent: March 30, 2021Assignee: Marvell Asia Pte, Ltd.Inventors: Zhewei Jiang, Muhammed Ahosan UL Karim, Xi Cao, Vivek Joshi, Jack M. Higman
-
Publication number: 20200342921Abstract: Disclosed is a three-port static random access memory (3P-SRAM) that performs XNOR operations. The cell has a write port and first and second read ports. Read operations are enabled through either the first read port using a first read wordline and a common read bitline or the second read port using a second read wordline and the common read bitline. Read wordline activation is controlled such that only one read wordline is activated (i.e., receives a read pulse) at a time. As a result, a read operation through either read port effectively accomplishes an XNOR operation. Also disclosed is a memory array, which incorporates such cells and which performs XNOR-bitcount-compare functions. Since XNOR-bitcount-compare functions are used in XNOR-NET type binary neural networks (BNNs), the memory array can be employed for implementing such a BNN designed for improved performance, scalability, and manufacturability. Also disclosed is an in-memory computing method.Type: ApplicationFiled: April 25, 2019Publication date: October 29, 2020Inventors: Zhewei Jiang, Muhammed Ahosan UL Karim, Xi Cao, Vivek Joshi, Jack M. Higman
-
Patent number: 8638592Abstract: An SRAM has at least two sets of pass transistors for coupling at least two sets of bit lines to true and complement data nodes of an SRAM cell based on the assertion of at least two word lines. The cell includes two pull up transistors and two pull down transistors coupled to the true and complement data nodes. None of the pass transistors are implemented in an active area that includes a pull up transistor or a pull down transistor of the cell.Type: GrantFiled: September 8, 2011Date of Patent: January 28, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Sayeed A. Badrudduza, Jack M. Higman, Sanjay R. Parihar
-
Patent number: 8431970Abstract: An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor.Type: GrantFiled: September 17, 2010Date of Patent: April 30, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Ertugrul Demircan, Jack M. Higman
-
Publication number: 20130064003Abstract: An SRAM has at least two sets of pass transistors for coupling at least two sets of bit lines to true and complement data nodes of an SRAM cell based on the assertion of at least two word lines. The cell includes two pull up transistors and two pull down transistors coupled to the true and complement data nodes. None of the pass transistors are implemented in an active area that includes a pull up transistor or a pull down transistor of the cell.Type: ApplicationFiled: September 8, 2011Publication date: March 14, 2013Inventors: Sayeed A. Badrudduza, Jack M. Higman, Sanjay R. Parihar
-
Patent number: 8315117Abstract: A memory and method for access the memory are provided. A first test is used to test memory elements to determine a lowest power supply voltage at which all the memory elements will operate to determine a weak memory element. Redundancy is used to substitute a redundant memory element for the weak memory element. The weak memory element is designated as a test element. In response to receiving a request to change a power supply voltage provided to the memory elements, a second test is used to test the test element to determine if the test element will function correctly at a new power supply voltage. If the test element passes the second test, the memory elements are accessed at the new power supply voltage. If the test element fails the second test, the memory elements are accessed using an access assist operation.Type: GrantFiled: March 31, 2009Date of Patent: November 20, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Shayan Zhang, Troy L. Cooper, Jack M. Higman, Prashant U. Kenkare, Andrew C. Russell
-
Patent number: 8183639Abstract: A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions.Type: GrantFiled: October 7, 2010Date of Patent: May 22, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Pierre Malinge, Jack M. Higman, Sanjay R. Parihar
-
Publication number: 20120086082Abstract: A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions.Type: ApplicationFiled: October 7, 2010Publication date: April 12, 2012Inventors: PIERRE MALINGE, JACK M. HIGMAN, SANJAY R. PARIHAR
-
Patent number: 8009489Abstract: A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors includes a first transistor and a second transistor. In one embodiment, the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier. A write back circuit is coupled to an output of the sense amplifier. The write back circuit writes back to the memory cell a value read from the memory cell during a read cycle.Type: GrantFiled: May 28, 2009Date of Patent: August 30, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Shayan Zhang, Jack M. Higman, Prashant U. Kenkare, Pelley H. Perry, Andrew C. Russell
-
Publication number: 20110001214Abstract: An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor.Type: ApplicationFiled: September 17, 2010Publication date: January 6, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: ERTUGRUL DEMIRCAN, JACK M. HIGMAN
-
Patent number: 7852692Abstract: Test circuitry for determining whether a memory can operate at a lower operating voltage. The test circuitry includes a sense circuit having a delayed sensing characteristic as compared to other sense amplifier circuits of the memory. With this circuitry, the test circuitry can determine if the sense circuit can provide valid data under more severe sensing conditions. In one example, the sense circuit includes a delay circuit in the sense enable signal path. If sense circuit can provide data at more server operating conditions, then the memory operating voltage can be lowered.Type: GrantFiled: June 30, 2008Date of Patent: December 14, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Shayan Zhang, Jack M. Higman, Michael D. Snyder
-
Publication number: 20100302837Abstract: A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors includes a first transistor and a second transistor. In one embodiment, the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier. A write back circuit is coupled to an output of the sense amplifier. The write back circuit writes back to the memory cell a value read from the memory cell during a read cycle.Type: ApplicationFiled: May 28, 2009Publication date: December 2, 2010Inventors: Shayan Zhang, Jack M. Higman, Prashant U. Kenkare, Pelley H. Perry, Andrew C. Russell
-
Patent number: 7820520Abstract: An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor.Type: GrantFiled: March 22, 2007Date of Patent: October 26, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Ertugrul Demircan, Jack M. Higman
-
Publication number: 20100246298Abstract: A memory and method for access the memory are provided. A first test is used to test memory elements to determine a lowest power supply voltage at which all the memory elements will operate to determine a weak memory element. Redundancy is used to substitute a redundant memory element for the weak memory element. The weak memory element is designated as a test element. In response to receiving a request to change a power supply voltage provided to the memory elements, a second test is used to test the test element to determine if the test element will function correctly at a new power supply voltage. If the test element passes the second test, the memory elements are accessed at the new power supply voltage. If the test element fails the second test, the memory elements are accessed using an access assist operation.Type: ApplicationFiled: March 31, 2009Publication date: September 30, 2010Inventors: Shayan Zhang, Troy L. Cooper, Jack M. Higman, Prashant U. Kenkare, Andrew C. Russell
-
Publication number: 20090323446Abstract: Test circuitry for determining whether a memory can operate at a lower operating voltage. The test circuitry includes a sense circuit having a delayed sensing characteristic as compared to other sense amplifier circuits of the memory. With this circuitry the test circuitry can determine if the sense circuit can provide valid data under more severe sensing conditions. In one example, the sense circuit includes a delay circuit in the sense enable signal path. If sense circuit can provide data at more server operating conditions, then the memory operating voltage can be lowered.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Inventors: SHAYAN ZHANG, JACK M. HIGMAN, MICHAEL D. SNYDER
-
Patent number: 7609541Abstract: A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further includes a first inverter having an input terminal coupled to the first storage node, an output terminal, and a first power supply voltage terminal for receiving a first power supply voltage. The memory cell further includes a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter at the first storage node, and a second power supply voltage terminal for receiving a second power supply voltage, wherein the second power supply voltage is varied relative to the first power supply voltage during a write operation to the memory cell.Type: GrantFiled: December 27, 2006Date of Patent: October 27, 2009Assignee: Freescale Semiconductor, Inc.Inventors: James David Burnett, Glenn C. Abeln, Jack M. Higman
-
Patent number: 7483327Abstract: A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter based on the relative speed. In one embodiment, an integrated circuit may include a ring oscillator, a shift register having a clock input coupled to an output of the ring oscillator, and compare logic coupled to an output of the shift register. The shift register is enabled in response to initiating a memory access to a memory and disabled in response to completing the memory access. The compare logic provides a relative speed indicator representative of a relative speed of the memory.Type: GrantFiled: March 2, 2006Date of Patent: January 27, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Qadeer A. Qureshi, James D. Burnett, Jack M. Higman, Thomas Jew
-
Patent number: 7440313Abstract: A two-port SRAM memory cell includes a pair of cross-coupled inverters coupled to storage nodes. An access transistor is coupled between each storage node and a write bit line and controlled by a write word line. The write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters. During a write operation, the write word line is asserted. A voltage at the power supply terminal of the cross-coupled inverters follows the write word line voltage, thus making it easier for the stored logic state at the storage nodes to change, if necessary. At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters to function normally and hold the logic state of the storage node. Coupling the power supply node of the cross-coupled inverters allows faster write operations without harming cell stability.Type: GrantFiled: November 17, 2006Date of Patent: October 21, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Glenn C. Abeln, James D. Burnett, Lawrence N. Herr, Jack M. Higman
-
Publication number: 20080230873Abstract: An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor.Type: ApplicationFiled: March 22, 2007Publication date: September 25, 2008Inventors: Ertugrul Demircan, Jack M. Higman
-
Publication number: 20080158938Abstract: A memory cell including an access transistor coupled to a first storage node and a read port coupled to one of the first storage node or a second storage node is provided. The memory cell further includes a first inverter having an input terminal coupled to the first storage node, an output terminal, and a first power supply voltage terminal for receiving a first power supply voltage. The memory cell further includes a second inverter having an input terminal coupled to the output terminal of the first inverter, an output terminal coupled to the input terminal of the first inverter at the first storage node, and a second power supply voltage terminal for receiving a second power supply voltage, wherein the second power supply voltage is varied relative to the first power supply voltage during a write operation to the memory cell.Type: ApplicationFiled: December 27, 2006Publication date: July 3, 2008Inventors: James David Burnett, Glenn C. Abeln, Jack M. Higman