Patents by Inventor Jack Mateosky

Jack Mateosky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for mapping and multiplexing wider clock tolerance signals in optical transport network transponders and multiplexers
    Patent number: 7602814
    Abstract: The present invention provides systems and methods for mapping and multiplexing wider clock tolerance signals in Optical Transport Network (OTN) transponders and multiplexers. In one exemplary embodiment, the present invention allows wide tolerance signals, such as a 10 GbE with a ±100 PPM clock tolerance, to be 100% transparently mapped asynchronously into OTU2-LAN rate transport signals. In another exemplary embodiment, the present invention allows wide tolerance signals, such as a 10 GbE with a ±100 PPM clock tolerance, to be 100% transparently multiplexed asynchronously in to OTU3-LAN rate transport signals. The present invention utilizes extra Negative Justification Opportunities (NJO) in either unused OPUk overhead or in OPUk payload area and Positive Justification Opportunities (PJO) in OPUk payload area. Advantageously, the extra NJO and PJO provide additional bandwidth for client data rate offsets beyond OTN specifications.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: October 13, 2009
    Assignee: Ciena Corporation
    Inventors: Kevin S. Meagher, Jack Mateosky, Steven A. Surek
  • Systems and methods for mapping and multiplexing wider clock tolerance signals in optical transport network transponders and multiplexers
    Publication number: 20080267223
    Abstract: The present invention provides systems and methods for mapping and multiplexing wider clock tolerance signals in Optical Transport Network (OTN) transponders and multiplexers. In one exemplary embodiment, the present invention allows wide tolerance signals, such as a 10 GbE with a ±100 PPM clock tolerance, to be 100% transparently mapped asynchronously into OTU2-LAN rate transport signals. In another exemplary embodiment, the present invention allows wide tolerance signals, such as a 10 GbE with a ±100 PPM clock tolerance, to be 100% transparently multiplexed asynchronously in to OTU3-LAN rate transport signals. The present invention utilizes extra Negative Justification Opportunities (NJO) in either unused OPUk overhead or in OPUk payload area and Positive Justification Opportunities (PJO) in OPUk payload area. Advantageously, the extra NJO and PJO provide additional bandwidth for client data rate offsets beyond OTN specifications.
    Type: Application
    Filed: April 30, 2007
    Publication date: October 30, 2008
    Inventors: Kevin S. Meagher, Jack Mateosky, Steven A. Surek