Abstract: A method is provided for use with a packet routing network in which one or more endpoints includes Flash storage; multiple endpoints are configured to impart services to packets; a distributed routing structure is provided that includes routing structure portions that are associated with endpoints and that indicate next hop destination endpoint addresses that collectively define multiple sequences of endpoints that each includes one or more endpoints configured to impart a service and an endpoint that includes Flash storage; packets received from an external network are propagated through defined sequences of endpoints; services are imparted to a received packet by endpoints that receive it in the course of its propagation.

Abstract: A system is provided that includes a packet routing network that includes routing circuitry to route packets between endpoints coupled to the network; one or more endpoints include a Flash storage circuit; a distributed routing structure defines multiple routes, each route including a different sequence of endpoints, including a Flash storage circuit endpoint; the distributed endpoint routing structure includes routing structure portions that are distributed among endpoints; the endpoints provide services to packets transmitted over routes defined by the distributed routing structure.

Abstract: A system can comprise an I/O circuitry, a processor, reconfigurable circuitry, an array of flash storage devices, and a serial interconnect network that is coupled to transfer data between the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The processor can be configured to designate an interconnect address space for use in communication over the interconnect network among the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The reconfigurable circuitry can be configured to translate data addresses during transfers of data between the I/O circuitry and the array of flash storage devices. A method to access an array of flash storage devices that are coupled to I/O circuitry over a serial interconnect network can comprise using reconfigurable circuitry to capture data during transfers of data over the serial interconnect network.

Abstract: A method is provided to configure endpoints of a packet routing network, in which one or more endpoints includes Flash storage; multiple endpoints are provided that are configured to impart services to packets; a plurality of information structure portions are provided that associate flow identifiers with next hop destination endpoint addresses to define a plurality of flow identifier-next hop destination endpoint addresses pairs (pairs); different pairs are stored within non-transitory storage devices at different endpoints so that relationships among the next hop destination endpoint addresses of the pairs stored at different endpoints define multiple respective sequences of endpoints that each includes one or more endpoints configured to impart a service and an endpoint that includes Flash storage.

Abstract: A system can comprise an I/O circuitry, a processor, reconfigurable circuitry, an array of flash storage devices, and a serial interconnect network that is coupled to transfer data between the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The processor can be configured to designate an interconnect address space for use in communication over the interconnect network among the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The reconfigurable circuitry can be configured to translate data addresses during transfers of data between the I/O circuitry and the array of flash storage devices. A method to access an array of flash storage devices that are coupled to I/O circuitry over a serial interconnect network can comprise using reconfigurable circuitry to capture data during transfers of data over the serial interconnect network.

Abstract: A system can comprise an I/O circuitry, a processor, reconfigurable circuitry, an array of flash storage devices, and a serial interconnect network that is coupled to transfer data between the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The processor can be configured to designate an interconnect address space for use in communication over the interconnect network among the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The reconfigurable circuitry can be configured to translate data addresses during transfers of data between the I/O circuitry and the array of flash storage devices. A method to access an array of flash storage devices that are coupled to I/O circuitry over a serial interconnect network can comprise using reconfigurable circuitry to capture data during transfers of data over the serial interconnect network.

Abstract: Apparatus and method for accelerating processing operations of flash based storage systems are disclosed herein. In some embodiments, an IC component disposed between I/O circuitry and flash storage devices is configured to optimize fulfillment of data read and write requests originating from a network or device external to the flash based storage system using cache memory before involving the flash storage devices.

Abstract: Apparatus and method for accelerating processing operations of flash based storage systems are disclosed herein. In some embodiments, an IC component disposed between I/O circuitry and flash storage devices is configured to optimize fulfillment of data read and write requests originating from a network or device external to the flash based storage system using cache memory before involving the flash storage devices.

Abstract: A system can comprise an I/O circuitry, a processor, reconfigurable circuitry, an array of flash storage devices, and a serial interconnect network that is coupled to transfer data between the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The processor can be configured to designate an interconnect address space for use in communication over the interconnect network among the I/O circuitry, the processor, the reconfigurable circuitry and the flash storage devices. The reconfigurable circuitry can be configured to translate data addresses during transfers of data between the I/O circuitry and the array of flash storage devices. A method to access an array of flash storage devices that are coupled to I/O circuitry over a serial interconnect network can comprise using reconfigurable circuitry to capture data during transfers of data over the serial interconnect network.

Abstract: Apparatus and method for accelerating processing operations of flash based storage systems are disclosed herein. In some embodiments, an IC component disposed between I/O circuitry and flash storage devices is configured to optimize fulfillment of data read and write requests originating from a network or device external to the flash based storage system using cache memory before involving the flash storage devices.

Abstract: Optically active N-3-(4-substituted phenyl)propyl-.beta.-phenethanolamines are provided as well as pharmaceutical compositions containing such compounds. A method for effecting weight control in obese animals utilizing optically active phenethanolamine is disclosed. Novel intermediates useful in the preparation of optically active .beta.-phenethanolamines are provided.

Abstract: Optically active N-3-(4-substituted phenyl)propyl-.beta.-phenethanolamines are provided as well as pharmaceutical compositions containing such compounds. A method for effecting weight control in obese animals utilizing optically active phenethanolamines is disclosed. Novel intermediates useful in the preparation of optically active .beta.-phenethanolamines are provided.

Abstract: A nest of folds of decorative wrapping paper. Each fold includes at least one sheet of wrapping paper which has one printed decorative surface and one unprinted surface. A first fold of paper is creased longitudinally into a flat V-shaped configuration having two panels of approximately equal width. A second fold of paper is creased longitudinally into a flat Z-shaped configuration having three panels. These three panels include a center panel having the same width as a panel of the first fold and two side panels, one of which is one-third and the other of which is two-thirds as wide as the center panel. A third panel is creased in the same configuration as the second fold.

Abstract: N-Mono or dihydroxyphenylalkyl dopamine derivatives and salts thereof are inotropic agents useful in a method for treatment of acutely depressed cardiac insufficiency.