Abstract: A signal generator provides circular addressing, i.e., performs basic modulo boundary indexing, which includes both positive and negative addressing, by adding an increment to a base register until a modulo boundary is reached without permitting the carry bit to propagate but instead resetting the address back to its lowest value. More particularly, the invention provides a signal generator which includes an adder having base address signals applied thereto from one of a plurality of registers and having an operand such as signals from an instruction data register (IDR) also applied thereto. Selected most significant bits from the output of the adder are applied to the input of a modulo mask function unit. Also applied to the input of the modulo mask function is a number of most significant bits of the base address signal. The carry bit from the adder is also applied to the input of the modulo mask function unit.