Abstract: An aircraft control mechanism for a speed brake includes a shaft, an outer sleeve surrounding the shaft and a sprag clutch. The mechanism also includes input and output elements and a control element with the input element tied to the outer sleeve. The control element is tied to the shaft and the output is operatively connected to the output of the clutch. A control cable is connected to the output for moving a speed brake between a first and a second position. A manual input actuates the control element of the clutch. An automatic input is connected to the outer sleeve through a torsional dampening device which minimizes chatter or sticking due to high forces which are required to extricate the sprag clutch from a relatively high racked-in load.

Abstract: A system for monitoring, recording and displaying vehicle operating parameters is described, which is capable of simultaneously providing operating data for the driver, an on board summary of critical trip parameters, and storage of monitored vehicle operating data for subsequently generating reports off-line which describe in detail the selected trip information. The system consists of a Vehicle Mounted Unit [VMU] which accepts inputs from a variety of sensors. Using these inputs, the VMU continuously computes the various parameters in order to provide the operating data as well as the on board trip summary. Detailed data are simultaneously stored in the VMU memory for subsequent processing by an off-line computer. The contents of the VMU memory may be transferred to the computer in a variety of ways.

Abstract: The invention relates to a dedicated microprocessor for an electronic taximeter, and a taximeter including the microprocessor. The microprocessor includes, (a) a main memory for storing data at a plurality of storage locations therein; (b) a data memory for receiving input data at a plurality of storage locations therein; (c) a combiner for combining the data storage locations of the main memory with the input data of respective storage locations of the data memory for updating the main memory; (d) a program memory for controlling the operation of the data memory, and comprising a plurality of storage locations therein; (e) a counter for sequentially selecting the storage locations of the main memory and the program memory; and (f) clock means for driving the counter means through its cycle. The main memory means is preferably a random access memory (RAM), and the data memory means and the program memory means can comprise, respectively, first and second read only memory (ROM) means.