Patents by Inventor Jack T Ma

Jack T Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113161
    Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).
    Type: Application
    Filed: December 14, 2023
    Publication date: April 4, 2024
    Inventors: Willy RACHMADY, Cheng-Ying HUANG, Matthew V. METZ, Nicholas G. MINUTILLO, Sean T. MA, Anand S. MURTHY, Jack T. KAVALIEROS, Tahir GHANI, Gilbert DEWEY
  • Publication number: 20240105852
    Abstract: Top-gate thin film transistor (TFTs) structures. Thin film transistors when in the top-gate configuration suffer from contact resistance. An example TFT includes a semiconductor layer doped with one or more dopant elements. A gate dielectric layer is on the semiconductor layer, and a gate electrode is on the gate dielectric layer. The semiconductor layer is doped with the one or more dopant elements beneath the gate dielectric layer. The TFT may further include one or more contacts and/or one or more gate spacers, and the semiconductor layer may further be doped with the one or more dopant elements beneath the contact(s) and/or gate spacer(s).
    Type: Application
    Filed: December 8, 2023
    Publication date: March 28, 2024
    Applicant: Intel Corporation
    Inventors: Abhishek A. Sharma, Sean T. Ma, Van H. Le, Jack T. Kavalieros, Gilbert Dewey
  • Patent number: 11929435
    Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: March 12, 2024
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Willy Rachmady, Jack T. Kavalieros, Cheng-Ying Huang, Matthew V. Metz, Sean T. Ma, Harold Kennel, Tahir Ghani
  • Patent number: 11923410
    Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey
  • Patent number: 11754750
    Abstract: A method and system is presented for short to long-term flood forecasting. At the core of the method is a neural network-based flood forecasting model. The method and system performs the steps to implement and use the neural network-based flood forecasting model comprising obtaining historical data from the region, including but not limited to climate and water level data; sampling and structuring the historical data in conjunction with data queried from a GIS (geographic information system) into a dataset; dividing the dataset into pre-processed training and validation partitions; configuring the neural network and training hyperparameters; training the neural network-based flood forecasting model on the pre-processed training partition; performing validation on the neural network-based flood forecasting model with the pre-processed validation partition. Embodiments of the invention are capable of performing flood forecasting over a region in short to long-term time intervals.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: September 12, 2023
    Assignee: ENTROPIC INNOVATION LLC
    Inventor: Jack T Ma