Abstract: A floating point number which includes a mantissa field, an exponent field, and a sign field is converted to an integer of n-bit size including a sign bit. The sign field is examined to determine if the floating point number is a positive or negative number. The mantissa field is shifted right to thereby denormalize the mantissa resulting in a shifted mantissa. If the floating point number is a negative number, zero is subtracted from the shifted mantissa to produce a result mantissa field that is a two's complement number. Otherwise, zero is added to the shifted mantissa to produce a result mantissa field. Overflow or underflow of the result mantissa field with respect to the integer of n-bit size is detected and the sign bit is set appropriately to reflect the fact that the sign field of the floating point number is a negative or positive number.

Abstract: A parallel carry and carry propagation generator for use with a modulo-2 N-bit operand adder generates the required carry bits to complete the N-bit pair modulo-2 sums as a parallel operation. The logic structure has log.sub.2 2N operation levels that allow for constant fan-in and fan-out design as well as static, rather than fixed-rate precharge/discharge, operation. A simplified version of the network is also suitable for use as a conditional sum selection controller for a conditional sum adder.

Abstract: Multistage leading zero detection is used in a left-shift normalization unit for normalizing floating-point mantissas. Detection of the leading one is accomplished by segmenting the mantissa into non-overlapping segments. The most significant segment containing a non-zero value bit is detected producing a fully decoded output in which an output line is activated corresponding to the segment position within the mantissa where the leading one has been detected. A second level of detection selects the designated most significant segment and detects the position of the most significant non-zero bit within the segment producing a fully decoded output and, in turn, causes the activation of a line within a second set of lines that corresponds to the leading one bit position within the segment.