Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to a single path memory sense amplifier circuit and methods of manufacture. The circuit includes a sense amplifier circuit comprising a plurality of self-aligned transistors in a single sensing path; and a memory array connected to the sense amplifier circuit by the single sensing path.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to a single path memory sense amplifier circuit and methods of manufacture. The circuit includes a sense amplifier circuit comprising a plurality of self-aligned transistors in a single sensing path; and a memory array connected to the sense amplifier circuit by the single sensing path.

Abstract: The present disclosure relates to a structure which includes a merged write driver circuit with a first device next to a first memory array and a second device next to a second memory array, and the merged write driver circuit being configured to share a write driver line between the first device and the second device.

Abstract: The present disclosure relates to a structure which includes a merged write driver circuit with a first device next to a first memory array and a second device next to a second memory array, and the merged write driver circuit being configured to share a write driver line between the first device and the second device.

Abstract: In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks adapted to precondition registers within the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.

Abstract: Systems and methods are directed to verification of configuration data stored in memory cells. For example, in one embodiment, an integrated circuit such as a programmable logic device includes a plurality of non-volatile memory cells and a plurality of volatile memory cells adapted to receive and store data provided from the plurality of non-volatile memory cells. A comparator is adapted to compare stored data from the plurality of volatile memory cells with the data values of the plurality of non-volatile memory cells. Control circuitry is responsive to the comparator to control whether configuration data from the plurality of non-volatile memory cells is loaded to the plurality of volatile memory cells.

Abstract: In accordance with an embodiment of the present invention, a programmable logic device (PLD, such as a field programmable gate array (FPGA)) includes a plurality of input/output blocks having boundary scan cells that are adapted to precondition registers within a logic area of the programmable logic device with desired signal values prior to release of control of the input/output blocks to user-defined logic provided by a reconfiguration.

Abstract: Systems and methods are directed to verification of configuration data stored in memory cells. For example, in one embodiment, an integrated circuit includes a first plurality of memory cells including a first set of test memory cells. A second plurality of memory cells is adapted to receive and store data provided from the first plurality of memory cells. The second plurality of memory cells include a second set of test memory cells corresponding to the first set of test memory cells. A comparator is adapted to compare stored data from the second set of test memory cells with the data values of the first set of test memory cells. Control circuitry is responsive to the comparator to control whether additional data from the first plurality of memory cells is loaded to the second plurality of memory cells.

Abstract: A logic array device has an array of plural interconnect resources including plural lines and plural switchbox areas, with an array of plural Variable Grain Blocks (VGB's) interspersed within the array of plural interconnect resources. The array of plural interconnect resources does not regularly include lines of single-length or shorter, and the array of plural interconnect resources does not regularly include switchbox areas that are spaced apart from one another by distances of a single-length or shorter. The single-length corresponds to a traverse of a continuous distance covering approximately one VGB.

Abstract: A tileable structure is provided for logic array devices. The tileable structure has a mirror-symmetrical arrangement of sets of logic blocks, common control sections for the logic block sets, surrounding interconnect lines, and switching areas at intersections of the interconnect lines.

Abstract: A cell array circuit for a programmable logic device is provided with split read and write lines in the memory cell. The circuit eliminates the need for pass gates in the speed path. The circuit includes steering logic, a row line driver circuit and a row decoder circuit to facilitate the different modes of operation of the cell array circuit.

Abstract: A gate clamping circuit is disclosed that includes a logic gate and a bias circuit arrangement. Through this clamping circuit the speed of operation of the circuit during both low to high and high-to-low transitions of the output signal are optimized while power consumption is minimized.

Abstract: An output buffer circuit is disclosed that minimizes propagation delay and crowbar current. This circuit receives a data input signal and provides an output signal. This circuit includes a pull-up transistor, a first pull-down transistor, a speed improvement circuit and a crowbar current reduction circuit. The speed improvement circuit comprises an inverter with small propagation delay coupled to a second pull-down transistor which is smaller than the first pull-down transistor. The speed improvement circuit minimizes the propagation delay of the circuit when the data input signals changes from a high logic level to a low logic level by speeding up the initial rate of fall of the output signal due to the fast turning on of the second small pull-down transistor which receives the data input signal quickly through the small-propagation-delay inverter. The crowbar current reduction circuit comprises a first crowbar current reduction transistor which is smaller than the pull-up transistor.

Abstract: A high speed multiple input NOR gate. In an illustrative embodiment, the invention includes a plurality of pull-down transistors for providing an output signal. A pull-up transistor is coupled to the plurality of pull-down transistors for providing a drive current. A regulator is coupled to the pull-up transistor for regulating the drive current in response to temperature and power supply voltage variation so as to maintain the speed of the output signal during a low-to-high transition of the output signal. In specific implementations, the NOR gate is designed to regulate the output signal so that a high level or a low level thereof is maintained at a predetermined level.

Abstract: A sense amplifier is provided that has improved speed from input to output, particularly during low-to-high transitions on the output and minimizes power consumption. By removing the product term window circuit from the critical node, the overall speed of the amplifier is maximized. In addition, circuitry is included to speed up low-to-high transitions, high-to-low transitions and provide increased noise immunity over temperature variations.

Abstract: An input buffer circuit is provided that has improved speed performance. The input buffer circuit has a voltage swing of V.sub.DD -V.sub.th to V.sub.SS. In so doing, the speed of the input buffer signal from input to output is significantly increased. In addition, the circuit also incorporates an additional current leaker transistor that limits the output high voltage from going above V.sub.DD -V.sub.th.