Abstract: Methods for controlling complementary dual displays for use with an electronic device are presented including: sending a video signal to a first display, wherein the first display is a refresh-based, high frame rate display; displaying the video signal on the first display; and printing a frame of the video signal to a second display, wherein the second display is a bistable, low frame rate display, the printing including, loading a portion of a current frame of the video signal into a frame buffer, and displaying the current frame of the video signal to a second display, such that a bistable static image is displayed on the second display.

Abstract: Electronic devices having complementary dual displays are presented, the electronic devices including: a first display, wherein the first display is a refresh-based, high frame rate display; a first display controller for outputting an internal video signal to the first display; a second display, wherein the second display is a bistable, low frame rate display; and a second display controller for outputting the internal video signal to the second display. In some embodiments, the devices further include: a number of user input interfaces for receiving a user input, wherein the number of user input interfaces are configured to control the second display; and a user input controller for generating a control signal based on the user input, the user input controller in electronic communication with the number of user input interfaces and a processing unit of the electronic device.

Abstract: Methods for controlling complementary dual displays for use with an electronic device are presented including: sending a video signal to a first display, wherein the first display is a low resolution, high frame rate display; displaying the video signal on the first display; and printing a frame of the video signal to a second display, wherein the second display is a high resolution, low frame rate display, the printing including, loading a portion of a current frame of the video signal into a frame buffer, and displaying the current frame of the video signal to a second display, such that a high resolution static image is displayed on the second display.

Abstract: Electronic devices having complementary dual displays are presented, the electronic devices including: a first display, wherein the first display is a low resolution, high frame rate display; a first display controller for outputting an internal video signal to the first display; a second display, wherein the second display is a high resolution, low frame rate display; and a second display controller for outputting the internal video signal to the second display. In some embodiments, the devices further include: a number of user input interfaces for receiving a user input, wherein the number of user input interfaces are configured to control the second display; and a user input controller for generating a control signal based on the user input, the user input controller in electronic communication with the number of user input interfaces and a processing unit of the electronic device.

Abstract: A message is received in a first form for communicating with a first DBMS wherein the first form comprises an internet message prefix and a data portion, the internet message prefix comprising routing information for a client. The message is modified into a second form wherein the client routing information is integrated into the data portion of the message and wherein the second form of the message is utilized to communicate with a second DBMS. A result message generated by the second DBMS is received wherein the result message comprises a result data portion, the result data portion including the routing information. The result message is modified to the first form wherein the result message comprises the internet message prefix, the internet message prefix comprising the client routing information obtained from the result data portion. In this manner, the result message may be routed to the client.

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract: A method to form a highly dense monolithic three dimensional memory array is provided. In preferred embodiments, conductive or semiconductor spacers can be formed, then used as hard masks to pattern underlying layers, forming features at sublithographic pitch. Methods of the invention minimize photomasking steps and thus simplify fabrication.

Abstract: An apparatus, system, and method are provided for sharing a cached security profile in a database environment. The apparatus, system, and method include a cache module for caching a security profile accessible to primary tasks and secondary tasks. An identification module is provided that distinguishes between primary tasks authorized to refresh the security profile and secondary tasks. A refresh module cooperates with the cache module and identification module to selectively refresh the security profile in response to a refresh request and expiration of the security profile such that an old version of the security profile is retained for use by secondary tasks until an execution window closes.

Abstract: An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate.

Abstract: Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control gate that wraps around it, thereby increasing the coupling between the two. In another form, an erase gate wraps around a relatively small projection in order to take advantage of sharp edges of the projection to promote tunneling of electrons from the floating to the erase gate. In each case, the control or floating gate is positioned within the area of the floating gate in one direction, thereby not requiring additional substrate area for such memory cells.

Abstract: A database server storing an authorization module and a rerouting module. The authorization module may be configured to define a second network interface module authorized to relay a response message queued in a hold queue associated with a first network interface module, where the response message is generated in response to a first request message. The rerouting module may be configured to route the response message from the hold queue to the second network interface module in response to a second request message requesting messages queued in the hold queue. The present invention thus enables delivery of requested queued messages despite failure of the request for such messages to correspond to the queue in which the messages are contained.

Abstract: Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell.

Abstract: Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a second trench portion, is filled with a deposited dielectric. The second trench portion is filled with a grown dielectric. Filling the lower trench portion by growing a dielectric material provides for an even distribution of dielectric material within the lower portion. Filling the upper trench portion by depositing a dielectric material provides for an even distribution of material in the upper portion while also protecting against encroachment of the dielectric into device channel regions, for example. Devices can be fabricated by etching the substrate to form the trench region after or as part of etching one or more layers formed above the substrate for the device.

Abstract: Self-aligned trench filling is used to isolate devices in high-density integrated circuits. A deep, narrow trench isolation region is formed in a substrate between devices. The trench region includes two trench portions. A first trench portion, located above a second trench portion, is filled with a deposited dielectric. The second trench portion is filled with a grown dielectric. Filling the lower trench portion by growing a dielectric material provides for an even distribution of dielectric material within the lower portion. Filling the upper trench portion by depositing a dielectric material provides for an even distribution of material in the upper portion while also protecting against encroachment of the dielectric into device channel regions, for example. Devices can be fabricated by etching the substrate to form the trench region after or as part of etching one or more layers formed above the substrate for the device.

Abstract: Self-aligned trench filling to isolate active regions in high-density integrated circuits is provided. A deep, narrow trench is etched into a substrate between active regions. The trench is filled by growing a suitable dielectric such as silicon dioxide. The oxide grows from the substrate to fill the trench and into the substrate to provide an oxide of greater width and depth than the trench. Storage elements for a NAND type flash memory system, for example, can be fabricated by etching the substrate to form the trench after or as part of etching to form NAND string active areas. This can ensure alignment of the NAND string active areas between isolation trenches. Because the dielectric growth process is self-limiting, an open area resulting from the etching process can be maintained between the active areas. A subsequently formed inter-gate dielectric layer and control gate layer can fill the open area to provide sidewall coupling between control gates and floating gates.

Abstract: An apparatus, system, and method are provided for automatically freeing locked server resources using a timeout value closely related to actual real-time message delays plus a delta value that can be adjusted at a plurality of levels. The levels include default, server, connection, and transaction. The apparatus includes a timer, a communication module, a computation module, and a lock handler. The timer determines a timeout value for communications from a client to a server. The communication module sends an output message to the client and locks a server resource in anticipation of an acknowledgement (ACK) message from the client. The computation module, which calculates an ACK timer, includes a difference between a send time and a current time. If no ACK message has been received from the client and the ACK timer exceeds the timeout value, the lock handler may free the locked server resource.

Abstract: An apparatus, system, and method are disclosed for directly accessing a database management system (“DBMS”). A client communication module is included to transmit a data call between a client and a client interface wherein the client interface resides within a database network. A DBMS communication module is included to transmit the data call between the client interface and a hierarchical DBMS on a host within the database network. The client interface and hierarchical DBMS are free of user-defined code.

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the columm direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract: Floating gate structures are disclosed which have a base field coupled with the substrate and a narrow projection extending from the base away from the substrate. In one form, surfaces of a relatively large projection provide an increased surface area for a control gate that wraps around it, thereby increasing the coupling between the two. In another form, an erase gate wraps around a relatively small projection in order to take advantage of sharp edges of the projection to promote tunneling of electrons from the floating to the erase gate. In each case, the control or floating gate is positioned within the area of the floating gate in one direction, thereby not requiring additional substrate area for such memory cells.

Abstract: An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously-elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate.