Patents by Inventor Jack Z. Peng
Jack Z. Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10510427Abstract: The present invention relates to the technical field of integrated circuits. Disclosed is a one-time programmable memory with a high reliability and a low reading voltage, comprising: a first MOS transistor, a second MOS transistor, and an antifuse component. A gate terminal of the first MOS transistor is connected to a second connecting line (WS), a first connection terminal of the first MOS transistor is connected to the antifuse component, the antifuse component is connected to a first connecting line (WP), and a second connection terminal of the first MOS transistor is connected to a third connecting line (BL). A first connection terminal of the second MOS transistor is connected to a fourth connecting line (BR), and a second connection terminal of the second MOS transistor is connected to a third connecting line (BL). The invention further comprises a voltage limiting device with a control terminal and two connection terminals.Type: GrantFiled: February 18, 2016Date of Patent: December 17, 2019Assignee: SICHUAN KILOWAY ELECTRONICS INC.Inventors: Xuyang Liao, Junhua Mao, Jack Z. Peng
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Patent number: 10504908Abstract: A high-reliability one-time programmable memory adopting series high voltage partition, which relates to integrated circuit technology and comprises a first MOS tube, a second MOS tube and an anti-fuse element, wherein a gate end of the first MOS tube is connected to a second connecting line (WS), a first connecting end of the first MOS tube is connected to a gate end of the second MOS tube and a voltage limiting device, and a second connecting end of the first MOS tube is connected to a third connecting line (BL); a first connecting end of the second MOS tube is connected to a fourth connecting line (BR), a second connecting end of the second MOS tube is connected to the third connecting line (BL), and a gate end of the second MOS tube is connected to the voltage limiting device and the second connecting end of the first MOS tube.Type: GrantFiled: February 18, 2016Date of Patent: December 10, 2019Assignee: SICHUAN KILOWAY ELECTRONICS INC.Inventors: Jack Z. Peng, Junhua Mao, Xuyang Liao
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Publication number: 20190341393Abstract: A high-reliability one-time programmable memory adopting series high voltage partition, which relates to integrated circuit technology and comprises a first MOS tube, a second MOS tube and an anti-fuse element, wherein a gate end of the first MOS tube is connected to a second connecting line (WS), a first connecting end of the first MOS tube is connected to a gate end of the second MOS tube and a voltage limiting device, and a second connecting end of the first MOS tube is connected to a third connecting line (BL); a first connecting end of the second. MOS tube is connected to a fourth connecting line (BR), a second connecting end of the second MOS tube is connected to the third connecting line (BL), and a gate end of the second MOS tube is connected to the voltage limiting device and the second connecting end of the first MOS tube.Type: ApplicationFiled: February 18, 2016Publication date: November 7, 2019Applicant: SICHUAN KILOWAY ELECTRONICS INC.Inventors: Jack Z. PENG, Junhua MAO, Xuyang LIAO
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Publication number: 20190341119Abstract: The present invention relates to the technical field of integrated circuits. Disclosed is a one-time programmable memory with a high reliability and a low reading voltage, comprising: a first MOS transistor, a second MOS transistor, and an antifuse component. A gate terminal of the first MOS transistor is connected to a second connecting line (WS), a first connection terminal of the first MOS transistor is connected to the antifuse component, the antifuse component is connected to a first connecting line (WP), and a second connection terminal of the first MOS transistor is connected to a third connecting line (BL). A first connection terminal of the second MOS transistor is connected to a fourth connecting line (BR), and a second connection terminal of the second MOS transistor is connected to a third connecting line (BL). The invention further comprises a voltage limiting device with a control terminal and two connection terminals.Type: ApplicationFiled: February 18, 2016Publication date: November 7, 2019Applicant: SICHUAN KILOWAY ELECTRONICS INC.Inventors: Xuyang LIAO, Junhua MAO, Jack Z. PENG
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Patent number: 8797820Abstract: A non-volatile memory cell using two transistors, a bit select and a sense device and an antifuse device. The antifuse device is implemented with a field-effect transistor operated to behave like an antifuse when the cell is selected and a modest programming voltage under 5.5 volts and a current under 5-?A is applied. Only a soft breakdown is needed in the thin gate oxide because a local sense transistor is used during read operations to detect the programming and amplify it for column sense amplifiers. Reading also only requires low voltages of about one volt.Type: GrantFiled: July 31, 2012Date of Patent: August 5, 2014Assignee: Chengdu Kiloway Electronics Inc.Inventors: Jack Z. Peng, David Fong
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Patent number: 8780660Abstract: A high density, low voltage, and low-power one time programmable (OTP) memory is based on core cells with a one transistor design. A CLEAN pulse is directed to a single shunt device at the output of the column decoder so spurious charges that may have been stored in the floating nodes can be cleaned up. Such arrangement also allows for the simultaneous initialization of bit lines, data lines, and sensing lines to zero. Core area layout size is substantially reduced, and operational power requirements are exceeding low making these particularly suitable in HF and UHF RFID applications.Type: GrantFiled: July 31, 2012Date of Patent: July 15, 2014Assignee: Chengdu Kiloway Electronics Inc.Inventor: Jack Z. Peng
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Publication number: 20130208525Abstract: A non-volatile memory cell uses two transistors only, a bit select and a sense device. Each cell further comprises an antifuse device implemented, for example, with a field-effect transistor operated to behave like an antifuse when the cell is selected and a modest programming voltage under 5.5 volts and under 5-?A is applied. Only a soft breakdown is needed in the thin gate oxide because a local sense transistor is used during read operations to detect the programming and amplify it for column sense amplifiers. Reading also only requires low voltages of about one volt.Type: ApplicationFiled: July 31, 2012Publication date: August 15, 2013Inventors: Jack Z. Peng, David Fong
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Publication number: 20130194885Abstract: A high density, low voltage, and low-power one time programmable (OTP) memory is based on core cells with a one transistor design. A CLEAN pulse is directed to a single shunt device at the output of the column decoder so spurious charges that may have been stored in the floating nodes can be cleaned up. Such arrangement also allows for the simultaneous initialization of bit lines, data lines, and sensing lines to zero. Core area layout size is substantially reduced, and operational power requirements are exceeding low making these particularly suitable in HF and UHF RFID applications.Type: ApplicationFiled: July 31, 2012Publication date: August 1, 2013Inventor: Jack Z. Peng
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Patent number: 8259518Abstract: A memory cell has at least two word lines and at least two bit lines. The cell also has a first select device being connected to at least one word line and one bit line and a gate capacitor element connected to at least one word line and the first select device. The cell also has a sense device being connected in series to the gate capacitor element and the first select device. The sense device is connected to at least two bit lines.Type: GrantFiled: June 8, 2010Date of Patent: September 4, 2012Assignee: Sichuan Kiloway Electronics Inc.Inventors: Jack Z. Peng, David Fong
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Publication number: 20110299344Abstract: A memory cell has at least two word lines and at least two bit lines. The cell also has a first select device being connected to at least one word line and one bit line and a gate capacitor element connected to at least one word line and the first select device. The cell also has a sense device being connected in series to the gate capacitor element and the first select device. The sense device is connected to at least two bit lines.Type: ApplicationFiled: June 8, 2010Publication date: December 8, 2011Inventors: Jack Z. Peng, David Fong
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Patent number: 7907465Abstract: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.Type: GrantFiled: October 9, 2009Date of Patent: March 15, 2011Assignee: Kilopass Technology, Inc.Inventors: Jack Z. Peng, David Fong, Glen A. Rosendale
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Publication number: 20100091545Abstract: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.Type: ApplicationFiled: October 9, 2009Publication date: April 15, 2010Inventors: Jack Z. Peng, David Fong, Glen A. Rosendale
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Patent number: 5587945Abstract: A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate and a second tunneling capacitor connected from the common floating gate to the source of the NMOS transistor. The tunneling capacitor includes a tunneling oxide region utilized to charge or discharge the floating gate during program or erase. The CMOS cell further includes a pass transistor with a source to drain path connecting the source of the NMOS transistor to a second control voltage.Type: GrantFiled: November 6, 1995Date of Patent: December 24, 1996Assignee: Advanced Micro Devices, Inc.Inventors: Jonathan Lin, Jack Z. Peng, Radu Barsan, Sunil Mehta