Abstract: The present disclosure provides a method for manufacturing a fully self-aligned high-density 3D multi-layer memory, which relates to the technical field of memory manufacturing. The method includes the following steps: 1) forming a base structure; 2) grooving the base structure; 3) filling an insulating medium in the division groove; 4) deep-hole etching the insulating medium in step 3 to form memory cell holes discretely arranged along the division groove, where the insulating medium is present between adjacent memory cell holes, and conductive medium layers and insulating medium layers of the base structure are exposed in the memory cell holes; and 5) disposing various layers of medium required by a preset memory structure layer by layer onto the inner walls of the memory cell holes. The semiconductor memory manufactured according to the present disclosure has high storage density.

Abstract: A semiconductor memory fabrication method and the semiconductor memory are involved in semiconductors production and fabrication processes. The semiconductor memory manufacturing method of the present invention includes the following steps: 1) Using a semiconductor integrated circuit manufacturing process, a basic memory module array being fabricated on a wafer where the basic memory modules have IO circuit interfaces; 2) Dicing the wafer to obtain memory chips; 3) Packaging the separated memory chip. In step 1), the IO circuit interfaces of the basic memory modules adjacent in the orthogonal directions are connected by interconnection lines; and according to the predetermined memory capacity, step 2) is to determine the number of basic memory modules contained in the chip and the position of the edge line of the memory chip so that the interconnections across the edge line are cut off so to separate the entire memory chip from the wafer by dicing along the edge line of the memory chip.

Abstract: A fabrication method of three-dimensional programmable memory includes: 1) forming a base structure; 2) trenching the base structure; 3) setting the preset memory structure layer by layer onto the inner wall of strip trench; 4) filling the core medium in the cavity of the strip trench to form core medium layer; 5) setting the isolation trenches and isolation trench holes to isolate the left-right fingers and memory units, respectively, where the isolation trenches encroach at least one memory medium layer at the strip trench, and form a curve by connecting with the strip trenches from end to end. The isolation holes are set at the strip trenches to divide the strip into at least three independent memory bodies and encroach the medium layers of the base structure near the long sides of the strip trenches; and 6) filling the isolation trenches and holes with insulating medium.

Abstract: A one time programmable OTP memory array and a read and write method thereof are provided. The OTP memory array according to the present disclosure includes M×N OTP memories, the OTP memories each include a storage MOS transistor, a first MOS transistor, a second MOS transistor and a detection MOS transistor, an isolation module is disposed between a control terminal of the detection MOS transistor and the storage MOS transistor; the isolation module includes at least one isolation MOS transistor; and in the array, a gate of each storage MOS transistor is connected to a same storage control point, each isolation MOS transistor is distinguished based on a distance from the storage MOS transistor, and gates of isolation MOS transistors with a same distance from the storage MOS transistor are connected to a same isolation control point.

Abstract: A method for manufacturing a high-density three-dimensional programmable memory, relating to the memory manufacturing technology, comprises the following steps: 1) forming a base structure; 2) grooving the base structure; 3) disposing, storage medium layers required by a preset memory structure layer by layer on an inner wall of the division groove; 4) filling a core medium in the division groove to form a core medium layer; 5) etching, through a mask etching process, to form deep holes along the separation division groove filled with the core where the deep holes truncate the core medium in the division groove; and 6) filling an insulation medium in the deep holes. The method has the beneficial effects of low costs and the highest storage density.

Abstract: A data storage device is involved in data storage technology. The data storage device of present invention includes a data memory which is placed in a hermetic housing, a power interface of the data memory which is connected to the wireless power transmission unit, and a data transmission interface of the data memory which is connected to the wireless data transmission unit. The wireless power transmission unit and the data transmission unit are placed in the housing. The present invention avoids the damage to the data memory due to the oxidation of the internal conductors.

Abstract: Fabrication method of three-dimensional programmable memory in this invention is related to the memory fabrication technology. The present invention includes the following steps: 1) forming a basic structure; 2) forming an interdigital structure on the basic structure; 3) forming the cylindrical memory unit: according to the preset memory structure, the required intermediate medium layer materials are set layer by layer onto the inner wall of the cylindrical trench hole, and finally the core medium material is filled in the cylindrical trench hole to form the core medium material layer. The beneficial effects of the present invention are that the prepared semiconductor memory has high memory density, low process cost, being easy to fabricate.

Abstract: A semiconductor memory fabrication method and the semiconductor memory are involved in semiconductors production and fabrication processes. The semiconductor memory manufacturing method of the present invention includes the following steps: 1) Using a semiconductor integrated circuit manufacturing process, a basic memory module array being fabricated on a wafer where the basic memory modules have IO circuit interfaces; 2) Dicing the wafer to obtain memory chips; 3) Packaging the separated memory chip. In step 1), the IO circuit interfaces of the basic memory modules adjacent in the orthogonal directions are connected by interconnection lines; and according to the predetermined memory capacity, step 2) is to determine the number of basic memory modules contained in the chip and the position of the edge line of the memory chip so that the interconnections across the edge line are cut off so to separate the entire memory chip from the wafer by dicing along the edge line of the memory chip.

Abstract: A method and fixture using magnetic field assisted self-alignment for chip packaging. Typical embodiments include a magnetic device having one or more pole groups, each pole group including two or three poles. Some embodiments provide multiple pole groups arranged in a one or two dimensional pole group array. The poles can build up a self-alignment magnetic field. The structure of fixture is simple and easy to implement. Typical embodiments can greatly reduce chip packaging cost and make packaging more efficient. In accordance with typical embodiments, a chip and a substrate can be self-aligned magnetically regardless of their shapes.

Abstract: A method and fixture using magnetic field assisted self-alignment for chip packaging. Typical embodiments include a magnetic device having one or more pole groups, each pole group including two or three poles. Some embodiments provide multiple pole groups arranged in a one or two dimensional pole group array. The poles can build up a self-alignment magnetic field. The structure of fixture is simple and easy to implement. Typical embodiments can greatly reduce chip packaging cost and make packaging more efficient. In accordance with typical embodiments, a chip and a substrate can be self-aligned magnetically regardless of their shapes.

Abstract: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs. Means are also provided for temporary data storage for design testing, etc. In alternative embodiments, using two differentially programmed fuses in a single memory cell, the selection and programming circuitry are merged.

Abstract: One-time programmable (OTP) nonvolatile fuse memory cells are disclosed that do not require decoding or addressing for reading their data content. Each fuse memory cell has its content latched at its output and available at all times and can be used, for example, for code storage memories, serial configuration memories, and as individual fuse bits for ID (identification), trimming, and other post-fabrication System-on-Chip (SoC) customization needs.

Abstract: Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.

Abstract: Methods and apparatus are disclosed to implement programmable logic generators that provide the advantages of compatible look-up tables (LUTs) while utilizing less silicon real estate and power for the same number of functions. The disclosed methods and apparatus employ programmable switches to emulate memory units that are used in LUTs and illustrate construction of 2- and 3-input LUTs as building blocks of other multi-input LUTs.

Abstract: Memory cells including an SRAM and an OTP memory unit that combine the advantages of both technologies and can be fabricated by standard CMOS manufacturing without additional masking. The concepts and details may be applied to and utilized in other systems requiring memory and/or employing other fabrication technologies. Among other advantages, the SRAM part of memory cells allows countless programming of the cell, which is useful, for example, during the prototyping. The OTP part is utilized to permanently program the memory cell by either using external data or the data already existing in the SRAM part of the cell. The value held by the OTP unit may also be written directly into the SRAM part of the cell.

Abstract: Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.

Abstract: A cell that can be used as a dynamic memory cell for storing data used in programming a field programmable gate array (FPGA) is disclosed. The cell comprises a select transistor having a gate, a source, and a drain, the gate connected to said write bitline, the source connected to a floating point node, and the drain connected to a row wordline. A sense device determines the data stored on the floating point node. Finally, switch that is controlled by the floating point node is provided.

Abstract: A method of programming a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises allowing current to flow through the data storage element until a predetermined current or voltage is detected. If the current or voltage exceeds a threshold, then the programming is deemed complete.

Abstract: A method of testing the programmability of a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises applying a test voltage across the data storage element. The select transistor is turned on. Finally, a current flow through the data storage element when the test voltage is applied is measured. A test positive signal is indicated if the current flow is greater than a reference.

Abstract: A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed p+ region to form a p-n diode in the substrate underlying the gate of the transistor. Further, the wordline is formed from a buried diffusion N+ layer while the column bitline is formed from a counterdoped polysilicon layer.