Abstract: A shift actuator for a transmission includes a drive assembly coupled with a selector interface. A transmission selector operates between a plurality of transmission settings. A threaded actuator is rotationally operated by the drive assembly. A carriage linearly operates along the threaded actuator to define a plurality of actuator positions that correspond to the transmission settings. An actuator arm extends between the carriage and the transmission selector to translate linear operation of the carriage to rotational operation of the transmission selector.

Abstract: The disclosure relates to on-ear headphones comprising at least one ear-cushion, the at least one ear-cushion defining an ear-surface configured to interface with a user's ear when the headphones are worn by the user, the ear-surface comprising a perforated area, the perforated area comprising a plurality of staggered elongated perforations.

Abstract: A shift actuator for a transmission includes a drive assembly coupled with a selector interface. A transmission selector operates between a plurality of transmission settings. A threaded actuator is rotationally operated by the drive assembly. A carriage linearly operates along the threaded actuator to define a plurality of actuator positions that correspond to the transmission settings. An actuator arm extends between the carriage and the transmission selector to translate linear operation of the carriage to rotational operation of the transmission selector.

Abstract: The disclosure relates to on-ear headphones comprising at least one ear-cushion, the at least one ear-cushion defining an ear-surface configured to interface with a user's ear when the headphones are worn by the user, the ear-surface comprising a perforated area, the perforated area comprising a plurality of staggered elongated perforations.

Abstract: The disclosure relates to a headband for a headset, the headband comprising a first strip and a second strip detachably assembled together. The first strip comprises at least one through opening and the second strip is detachably connected via the through opening to the first strip as a cover. The second strip comprises first and second parts at least partly covering the first strip. The disclosure further relates to a headset comprising a headband and a method for assembly of a headband for a headset.

Abstract: The disclosure relates to a headband for a headset, the headband comprising a first strip and a second strip detachably assembled together. The first strip comprises at least one through opening and the second strip is detachably connected via the through opening to the first strip as a cover. The second strip comprises first and second parts at least partly covering the first strip. The disclosure further relates to a headset comprising a headband and a method for assembly of a headband for a headset.

Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.

Abstract: A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.

Abstract: An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating.

Abstract: An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET. In an associated method of manufacturing the semiconductor device, a first source/drain region is formed in a semiconductor layer. A field-effect transistor gate region, including a channel and a gate electrode, is formed over the first source/drain region. A second source/drain region is then formed over the channel having the appropriate conductivity type.

Abstract: An architecture for creating multiple operating voltage MOSFETs. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and first and second spaced-apart doped regions formed in the surface. A third doped region forming a channel of different conductivity type than the first region is positioned over the first region. A fourth doped region of a different conductivity and forming a channel is positioned over the second region. The process of creating the gate structure for each of the two transistors allows for the formation of oxide layers of different thickness between the two transistors. The transistors are therefore capable of operating at different operating voltages (including different threshold voltages). Each transistor further includes fifth and sixth layers positioned respectively over the third and fourth regions and having an opposite conductivity type with respect to the third and fourth regions.