Abstract: A method for managing data transfer for a plurality of processors. Transfer messages exchanged between processor units and an external node in an integrity manager located in hardware in communication with the processor units and the external node are received. An exchange of the transfer messages is managed by the processor units with the external node based on a selected mode in mixed integrity modes such that redundantly calculated outputs from the processor units in a high integrity mode match.

Abstract: A method for synchronizing processor units. An external synchronizer is communicated with to determine whether an undesired amount of skew is present between a first processor unit and a second processor unit in communication with a synchronization system. The first processor unit is selectively directed to perform an action without generating a needed result such that the undesired amount of skew between the first processor unit and the second processor unit is reduced when the undesired amount of skew is present in the first processor unit. The first processor unit and the second processor unit are associated with each other for a high integrity mode in which integrity checks are performed on corresponding messages generated by the first processor unit and the second processor unit.

Abstract: A method for managing data transfer for a plurality of processors. Transfer messages exchanged between processor units and an external node in an integrity manager located in hardware in communication with the processor units and the external node are received. An exchange of the transfer messages is managed by the processor units with the external node based on a selected mode in mixed integrity modes such that redundantly calculated outputs from the processor units in a high integrity mode match.

Abstract: A method for synchronizing processor units. An external synchronizer is communicated with to determine whether an undesired amount of skew is present between a first processor unit and a second processor unit in communication with a synchronization system. The first processor unit is selectively directed to perform an action without generating a needed result such that the undesired amount of skew between the first processor unit and the second processor unit is reduced when the undesired amount of skew is present in the first processor unit. The first processor unit and the second processor unit are associated with each other for a high integrity mode in which integrity checks are performed on corresponding messages generated by the first processor unit and the second processor unit.

Abstract: An efficient configurable signal filter. The filter includes a first mechanism for receiving a first signal of a first type and a second signal of a second type. A second mechanism selectively filters the first signal during a first mode of operation, and filters the second signal during a second mode of operation. A third mechanism generates control signals. A fourth mechanism automatically configures the second mechanism to operate in the first mode of operation or the second mode of operation based on the control signals. In a specific embodiment, the first type of signal is characterized by a first rate, and the second type of signal is characterized by a second rate. The first signal and the second signal are digital ADC outputs. The second mechanism includes plural filter blocks, each having one or more Multiply-Accumulate (MAC) pipes. Each of the one or more MAC pipes include one or more MAC blocks that are each associated with a coefficient memory data structure of a coefficient memory.