Abstract: The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadline(s) and the estimates, context switching may or may not be triggered.

Abstract: The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadline(s) and the estimates, context switching may or may not be triggered.

Abstract: Disclosed techniques relate to power management by work distribution circuitry. In some embodiments, a graphics processor includes first and second graphics processor sub-units that respectively include distributed work queue circuitry configured to store graphics work and shader circuitry configured to execute instructions specified by stored graphics work in the sub-unit's distributed work queue circuitry. In some embodiments, work control circuitry includes queue access circuitry to access graphics work in multiple queues and distribution circuitry to assign portions of respective sets of graphics work accessed from the multiple queues to the first and second graphics processor sub-units for execution. In some embodiments, tracking circuitry tracks status of assigned sets of graphics work.

Abstract: Disclosed embodiments relate to submitting tasks to a graphics processor directly by a host processor. In some embodiments, a graphics processor includes control circuitry that schedules and distributes portions of sets of assigned graphics work to multiple different graphics processor sub-units. A processor may execute a driver program for the graphics processor and a program that coordinates with the driver program to send work to the graphics processor, including to: store, in memory circuitry, configuration register data and queued sets of graphics work to be executed by the graphics processor and transmit a signal, to the control circuitry of the graphics processor, to change status of queued sets of graphics work in the memory circuitry. In response to the signal, the control circuitry may schedule and distribute the queued sets of graphics work. This scheduling may be performed without assistance of a firmware processor, which may improve overall performance.

Abstract: Techniques are disclosed relating to power management in a processing circuit that includes a set of functional blocks and performance counter registers configured to store utilization values indicative of utilization of associated ones of the set of functional blocks. A register interface circuit is configured to periodically sample the processing circuit to obtain aggregated utilization values generated from utilization values stored in the performance counter registers and write the aggregated utilization values to the set of trace buffer. A power management processor is configured to utilize a set of information stored in the set of trace buffers to determine whether to change a performance state of the processing circuit, the set of information including time-domain and frequency-domain representations of utilization of the processing circuit. In other embodiments, a functional block that is a hardware limiter of the processing circuit may be determined.

Abstract: Disclosed techniques relate to scheduling sets of graphics work using queues. In some embodiments, tracking circuitry implements entries for multiple tracking slots for a graphics processor. Queue access circuitry may access a data structure in memory that specifies multiple queues, where each queue enqueues control information for multiple sets of graphics work. Queue select circuitry may select sets of graphics work from the data structure based on one or more selection parameters and store control information for selected sets of graphics work in tracking slots of the tracking slot circuitry. Distribution circuitry may assign portions of respective sets of graphics work from the tracking slots to graphics processor circuitry for execution.

Abstract: The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadline(s) and the estimates, the operating parameters of the GPU may be changed.

Abstract: The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadline(s) and the estimates, context switching may or may not be triggered.

Abstract: The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadline(s) and the estimates, the operating parameters of the GPU may be changed.

Abstract: The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadline(s) and the estimates, context switching may or may not be triggered.

Abstract: The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadline(s) and the estimates, the operating parameters of the GPU may be changed.

Abstract: The operation of a GPU is controlled based on one or more deadlines by which one or more GPU tasks must be completed and estimates of the time required to complete the execution of a first GPU task (which is currently being executed) and the time required to execute one or more other GPU tasks (which are not currently being executed). Based on a comparison between the deadline(s) and the estimates, context switching may or may not be triggered.