Patents by Inventor Jackson Ellis

Jackson Ellis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12430208
    Abstract: Systems and methods for a controller including controller memory and logic are presented herein. The logic is configured to control access to a persistent storage media and, in response to one or more commands, determine an intermediate parity value based on a first parity calculation by sending a uni-directional command to the persistent storage media. The logic is further configured to store, in the controller memory, the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second parity calculation.
    Type: Grant
    Filed: March 27, 2024
    Date of Patent: September 30, 2025
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Publication number: 20250199723
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a primary persistent storage with a first type of media and a nonvolatile memory buffer with a second type of media that is different from the first type of media, store metadata for incoming write data in the nonvolatile memory buffer, store other data for the incoming write data in the primary persistent storage, and provide both runtime and power-fail write atomicity for the incoming write data. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: February 28, 2025
    Publication date: June 19, 2025
    Inventors: Peng Li, Jawad Khan, Jackson Ellis, Sanjeev Trika
  • Patent number: 12260126
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a primary persistent storage with a first type of media and a nonvolatile memory buffer with a second type of media that is different from the first type of media, store metadata for incoming write data in the nonvolatile memory buffer, store other data for the incoming write data in the primary persistent storage, and provide both runtime and power-fail write atomicity for the incoming write data. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: March 27, 2024
    Date of Patent: March 25, 2025
    Assignee: SK hynix NAND Product Solutions Corp.
    Inventors: Peng Li, Jawad Khan, Jackson Ellis, Sanjeev Trika
  • Publication number: 20250036783
    Abstract: An apparatus is disclosed that includes a network interface device comprising processors to implement network interface device functionality and communication protocol engine circuitry, wherein the network interface device is to: receive a request to write data to a memory node communicably coupled to the network interface device; identify network information corresponding to the request, wherein the network information includes at least one of quality of service (QoS), physical function (PF), virtual function (VF), name space identifier (NSID), flow ID, service level objectives (SLOs), or process address space ID (PASID); identify characteristics of the memory node, wherein the characteristics include at least page size of the memory node; and cause the data to be coalesced with other data on the memory node based on the network information and the characteristics.
    Type: Application
    Filed: October 15, 2024
    Publication date: January 30, 2025
    Applicant: Intel Corporation
    Inventors: Daniel Biederman, Yadong Li, Hemant Koka, Jackson Ellis, Salma Johnson
  • Patent number: 12112055
    Abstract: An embodiment of an electronic storage system includes one or more storage drives, at least one or more of the storage drives supporting erasure coding (EC); and a controller including logic to control local access to the one or more storage drives. The controller, in response to a write command, is to for one or more storage drives, allocate an intermediate buffer in the storage drive's non-volatile memory (NVM) to store intermediate data. The controller is to issue commands to a first storage drive to read old data, compute the intermediate data of the first storage drive as XOR of the old data and new data received in the write command, and atomically write the intermediate data of the first storage drive to the intermediate buffer of the first storage drive and write the new data to the first storage drive's NVM. The controller is to read the intermediate data of the first storage drive from the intermediate buffer of the first storage drive.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: October 8, 2024
    Assignee: INTEL CORPORATION
    Inventors: Piotr Wysocki, Sanjeev N. Trika, Gregory B. Tucker, Jackson Ellis, Jonathan M. Hughes
  • Publication number: 20240329873
    Abstract: Examples described herein relate to a device that includes: a host interface; and circuitry to: based on allocation of a region in a buffer, wherein the buffer is associated with Non-volatile Memory Express over Fabrics (NVMe-oF) transactions: based on a first size of compressed data to be stored in the buffer, deallocate a portion of the region in the buffer and store the compressed data of the first size into a second portion of the region in the buffer and based on a second size of the compressed data to be stored in the buffer, utilize the allocated region in the buffer to store the compressed data of the second size.
    Type: Application
    Filed: June 6, 2024
    Publication date: October 3, 2024
    Inventors: Ho-Ming LEUNG, Salma Mirza JOHNSON, Jackson ELLIS, Daniel Christian BIEDERMAN
  • Publication number: 20240264774
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a primary persistent storage with a first type of media and a nonvolatile memory buffer with a second type of media that is different from the first type of media, store metadata for incoming write data in the nonvolatile memory buffer, store other data for the incoming write data in the primary persistent storage, and provide both runtime and power-fail write atomicity for the incoming write data. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 27, 2024
    Publication date: August 8, 2024
    Inventors: Peng Li, Jawad Khan, Jackson Ellis, Sanjeev Trika
  • Publication number: 20240241792
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control local access to a persistent storage media and, in response to one or more commands, to determine an intermediate parity value based on a first local parity calculation, locally store the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second local parity calculation. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Publication number: 20240211392
    Abstract: Examples described herein relate to circuitry to allocate an Non-volatile Memory Express (NVMe) bounce buffer in virtual memory that is associated with an NVMe command and perform an address translation to an NVMe bounce buffer based on receipt of a response to the NVMe command from an NVMe target. In some examples, the circuitry is to translate the virtual address to a physical address for the NVMe bounce buffer based on receipt of a response to the NVMe command from an NVMe target.
    Type: Application
    Filed: February 6, 2024
    Publication date: June 27, 2024
    Inventors: Salma Mirza JOHNSON, Jose NIELL, Bradley A. BURRES, Jackson ELLIS, Yadong LI, Jayaram BHAT, Tony HURSON
  • Patent number: 12019910
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a primary persistent storage with a first type of media and a nonvolatile memory buffer with a second type of media that is different from the first type of media, store metadata for incoming write data in the nonvolatile memory buffer, store other data for the incoming write data in the primary persistent storage, and provide both runtime and power-fail write atomicity for the incoming write data. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: June 25, 2024
    Assignee: SK hynix NAND Product Solutions Corp.
    Inventors: Peng Li, Jawad Khan, Jackson Ellis, Sanjeev Trika
  • Patent number: 11971782
    Abstract: Systems and methods for a controller including controller memory and logic are presented herein. The logic is configured to control access to a persistent storage media and, in response to one or more commands, the logic determines an intermediate parity value based on a first parity calculation, and using the intermediate parity value determines a final parity value based on the intermediate parity value and a second parity calculation. Determining the intermediate parity value includes sending a uni-directional command to read an old data value from an address indicated in the uni-directional command, perform an exclusive-or operation on the old data value and a new data value indicated in the uni-directional command to determine the intermediate parity value and store, in the persistent storage media, the intermediate parity value at a location associated to an index indicated in the uni-directional command.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 30, 2024
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Patent number: 11630779
    Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: April 18, 2023
    Assignee: Seagate Technology, LLC
    Inventors: Nitin Satishchandra Kabra, Jackson Ellis, Niranjan Anant Pol, Mark Ish
  • Publication number: 20230082403
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control local access to a persistent storage media and, in response to one or more commands, to determine an intermediate parity value based on a first local parity calculation, locally store the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second local parity calculation. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: February 20, 2020
    Publication date: March 16, 2023
    Inventors: Sanjeev Trika, Gregory Tucker, James Harris, Jonathan Hughes, Piotr Wysocki, Gang Cao, Qihua Dai, Benjamin Walker, Ziye Yang, Xiaodong Liu, Changpeng Liu, Jackson Ellis
  • Publication number: 20220075729
    Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.
    Type: Application
    Filed: November 17, 2021
    Publication date: March 10, 2022
    Inventors: Nitin Satishchandra Kabra, Jackson Ellis, Niranjan Anant Pol, Mark Ish
  • Patent number: 11221956
    Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: January 11, 2022
    Assignee: Seagate Technology LLC
    Inventors: Nitin Satishchandra Kabra, Jackson Ellis, Niranjan Anant Pol, Mark Ish
  • Publication number: 20200363997
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a primary persistent storage with a first type of media and a nonvolatile memory buffer with a second type of media that is different from the first type of media, store metadata for incoming write data in the nonvolatile memory buffer, store other data for the incoming write data in the primary persistent storage, and provide both runtime and power-fail write atomicity for the incoming write data. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: August 6, 2020
    Publication date: November 19, 2020
    Applicant: Intel Corporation
    Inventors: Peng Li, Jawad Khan, Jackson Ellis, Sanjeev Trika
  • Patent number: 10783119
    Abstract: A method includes compressing input data to form compressed data and comparing a size of the compressed data to a maximum allowed size determined from a fixed sector size for a lower tier of the multi-tier storage system and a minimum pad length for a pad that is stored in the same sector as the compressed data when the compressed data is migrated to the lower tier. When the size of the compressed data is greater than the maximum allowed size, the input data is stored instead of the compressed data in an upper tier of the multi-tier storage system.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: September 22, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Jackson Ellis, Jeffrey Munsil, Carl Forhan
  • Patent number: 10754555
    Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 25, 2020
    Assignee: Seagate Technology LLC
    Inventors: Timothy Canepa, Jeffrey Munsil, Jackson Ellis, Mark Ish
  • Publication number: 20200264800
    Abstract: An embodiment of an electronic storage system includes one or more storage drives, at least one or more of the storage drives supporting erasure coding (EC); and a controller including logic to control local access to the one or more storage drives. The controller, in response to a write command, is to for one or more storage drives, allocate an intermediate buffer in the storage drive's non-volatile memory (NVM) to store intermediate data. The controller is to issue commands to a first storage drive to read old data, compute the intermediate data of the first storage drive as XOR of the old data and new data received in the write command, and atomically write the intermediate data of the first storage drive to the intermediate buffer of the first storage drive and write the new data to the first storage drive's NVM. The controller is to read the intermediate data of the first storage drive from the intermediate buffer of the first storage drive.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Inventors: Piotr WYSOCKI, Sanjeev N. TRIKA, Gregory B. TUCKER, Jackson ELLIS, Jonathan M. HUGHES
  • Patent number: 10740251
    Abstract: The implementations described herein provide a hybrid drive with a storage capacity including solid-state drive (NAND) technology and hard disc drive (HDD) technology. A translation layer is stored in the solid-state drive and includes plurality of entries. Each entry of the plurality of entries corresponds to at least one logical data unit and includes a cache state indicating where the data corresponding to the logical data unit is located and whether the data is valid. The translation layer may be a multi-layer map that includes a sparse mapping scheme. In a sparse multi-layer map, entries are leaf entries or non-leaf entries. Leaf entries include a cache state for the corresponding logical data unit(s). Non-leaf entries may include a pointer to a lower level mapping for a plurality of logical data units.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: August 11, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Alex Tang, Leonid Baryudin, Timothy Canepa, Jackson Ellis