Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control local access to a persistent storage media and, in response to one or more commands, to determine an intermediate parity value based on a first local parity calculation, locally store the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second local parity calculation. Other embodiments are disclosed and claimed.

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a primary persistent storage with a first type of media and a nonvolatile memory buffer with a second type of media that is different from the first type of media, store metadata for incoming write data in the nonvolatile memory buffer, store other data for the incoming write data in the primary persistent storage, and provide both runtime and power-fail write atomicity for the incoming write data. Other embodiments are disclosed and claimed.

Abstract: A method includes compressing input data to form compressed data and comparing a size of the compressed data to a maximum allowed size determined from a fixed sector size for a lower tier of the multi-tier storage system and a minimum pad length for a pad that is stored in the same sector as the compressed data when the compressed data is migrated to the lower tier. When the size of the compressed data is greater than the maximum allowed size, the input data is stored instead of the compressed data in an upper tier of the multi-tier storage system.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

Abstract: An embodiment of an electronic storage system includes one or more storage drives, at least one or more of the storage drives supporting erasure coding (EC); and a controller including logic to control local access to the one or more storage drives. The controller, in response to a write command, is to for one or more storage drives, allocate an intermediate buffer in the storage drive's non-volatile memory (NVM) to store intermediate data. The controller is to issue commands to a first storage drive to read old data, compute the intermediate data of the first storage drive as XOR of the old data and new data received in the write command, and atomically write the intermediate data of the first storage drive to the intermediate buffer of the first storage drive and write the new data to the first storage drive's NVM. The controller is to read the intermediate data of the first storage drive from the intermediate buffer of the first storage drive.

Abstract: The implementations described herein provide a hybrid drive with a storage capacity including solid-state drive (NAND) technology and hard disc drive (HDD) technology. A translation layer is stored in the solid-state drive and includes plurality of entries. Each entry of the plurality of entries corresponds to at least one logical data unit and includes a cache state indicating where the data corresponding to the logical data unit is located and whether the data is valid. The translation layer may be a multi-layer map that includes a sparse mapping scheme. In a sparse multi-layer map, entries are leaf entries or non-leaf entries. Leaf entries include a cache state for the corresponding logical data unit(s). Non-leaf entries may include a pointer to a lower level mapping for a plurality of logical data units.

Abstract: A garbage collection method comprises selecting one or blocks in a SSD of a hybrid drive for garbage collection; determining a state of data of the one or more selected blocks, wherein the state suggests a location and temperature of data; and executing a garbage collection efficiency and caching efficiency action on the data of the one or more selected blocks based on the determined state. The garbage collection process may utilize the state information provided by the cache layer of the hybrid drive to make decisions regarding data in the one or more selected blocks.

Abstract: A solid-state drive that can service multiple users or tenants and workloads (that is, multiple tenants) by enabling assigned bandwidth share of the solid-state drive across tenants is provided. The assigned bandwidth share is enabled for command submissions within a same assigned domain in addition to a weighted bandwidth share and quality of service control across different domains from all tenants.

Abstract: A computing device may accumulate behavior parameters of a controller or media with an authentication module of the controller prior to generating a unique signature with the authentication module. The unique signature can then be verified responsive to an initialization command from a host device before data is transferred by the controller between the host device and the media in response to the controller issuing at least one data access command.

Abstract: A method includes configuring a first set of blocks of a plurality of blocks of an IC chip as secure data blocks, and configuring a second set of blocks of the plurality of blocks as non-secure data blocks. The method further includes receiving a test mode entry request in the IC chip. In response to the IC chip receiving the test mode entry request, carrying out a data-initialization operation on the plurality of blocks independently of whether any blocks of the plurality of blocks are configured as the secure data blocks or the non-secure data blocks. An IC chip data output is disabled during the data-initialization operation.

Abstract: A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

Abstract: Implementations described and claimed herein provide a method and system for adaptive caching in a storage device. The method includes receiving an adaptive caching policy from a host for caching host read data and host write data in a hybrid drive using NAND cache, and allocating read cache for the host read data and write cache for the host write data in the NAND cache based on the adaptive caching policy. In some implementations, the method also includes iteratively performing an input/output (I/O) profiling operation to generate an I/O profile. An adaptive caching policy may be applied based on the I/O profile. When a unit time has completed, a new I/O profile may be compared with a current I/O profile. A new adaptive caching policy is applied based on determining the new I/O profile is different than the current I/O profile.

Abstract: A method includes compressing input data to form compressed data and comparing a size of the compressed data to a maximum allowed size determined from a fixed sector size for a lower tier of the multi-tier storage system and a minimum pad length for a pad that is stored in the same sector as the compressed data when the compressed data is migrated to the lower tier. When the size of the compressed data is greater than the maximum allowed size, the input data is stored instead of the compressed data in an upper tier of the multi-tier storage system.

Abstract: A method includes configuring a first set of blocks of a plurality of blocks of an IC chip as secure data blocks, and configuring a second set of blocks of the plurality of blocks as non-secure data blocks. The method further includes receiving a test mode entry request in the IC chip. In response to the IC chip receiving the test mode entry request, carrying out a data-initialization operation on the plurality of blocks independently of whether any blocks of the plurality of blocks are configured as the secure data blocks or the non-secure data blocks. An IC chip data output is disabled during the data-initialization operation.

Abstract: A data storage device can be configured with a data map that has one or more custom map attributes. A non-volatile memory of the data storage device may store data organized into a data map by a mapping module. The data map consisting of at least a data address translation and a custom attribute pertaining to an operational parameter of the data map with the custom attribute generated and maintained by the mapping module.

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.