Patents by Inventor Jackson Eng
Jackson Eng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145450Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a semiconductor package including a first surface, an opposing second surface, and a side wall. The electronic assembly may also include a printed circuit board coupled to the second surface of the semiconductor package. The electronic assembly may further include at least one passive component array including one or more passive components at least partially embedded in a mold layer, each passive component further including a first terminal and a second terminal, wherein the first terminal of the passive component may be coupled to the printed circuit board and the passive component array may be attached to the side wall of the semiconductor package.Type: ApplicationFiled: October 28, 2022Publication date: May 2, 2024Inventors: Chin Lee KUAN, Bok Eng CHEAH, Jackson Chung Peng KONG, Amit JAIN, Sameer SHEKHAR
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Publication number: 20240145420Abstract: The present disclosure generally relates to an electronic assembly. The electronic assembly may include a substrate including a plurality of first contact pads, a plurality of second contact pads, and a plurality of third contact pads. The electronic assembly may include a first device including a first footprint coupled to the substrate at a first surface. The electronic assembly may include a frame arranged between the first device and the substrate, the frame including a dielectric material, the frame further including a main frame extending around the first device, and further including a plurality of sub-frames encircling the plurality of first contact pads and the plurality of second contact pads on the substrate, wherein the frame may further include a conductive layer extending at least partially across the main frame.Type: ApplicationFiled: October 28, 2022Publication date: May 2, 2024Inventors: Bok Eng CHEAH, Seok Ling LIM, Kooi Chi OOI, Jackson Chung Peng KONG, Jenny Shio Yin ONG
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Publication number: 20240145365Abstract: A device is provided, including a dielectric layer, a plurality of first conductive segments within the dielectric layer and spaced apart from each other by respective first spacings, and a plurality of second conductive segments within the dielectric layer and spaced apart from each other by respective second spacings. The plurality of second conductive segments may be over and spaced apart from the plurality of first conductive segments by the dielectric layer. A respective one of the first conductive segments may at least partially extend across a corresponding one of the second spacings, and a respective one of the second conductive segments may at least partially extend across a corresponding one of the first spacings.Type: ApplicationFiled: October 28, 2022Publication date: May 2, 2024Inventors: Bok Eng CHEAH, Seok Ling LIM, Jenny Shio Yin ONG, Kooi Chi OOI, Jackson Chung Peng KONG
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Publication number: 20240145368Abstract: The present disclosure is directed to an electronic assembly and method of forming thereof. The electronic assembly may include a package substrate with a top substrate surface and an interposer coupled to the package substrate at the top substrate surface. The interposer may include a plurality of through interposer vias and an opening extending through the interposer. A power module may be arranged in the opening in the interposer and coupled to the package substrate at the top substrate surface. The power module may include a plurality of interconnects including a first interconnect coupled to a first voltage and a second interconnect coupled to a second voltage.Type: ApplicationFiled: October 28, 2022Publication date: May 2, 2024Inventors: Jackson Chung Peng KONG, Bok Eng CHEAH, Seok Ling LIM, Jenny Shio Yin ONG, Ravindra RUDRARAJU, Vijay KASTURI
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Publication number: 20240136269Abstract: A device is provided, including a package substrate including at least one opening extending through the package substrate, and an interconnect structure including a first segment and a second segment. The first segment may extend under a bottom surface of the package substrate and may further extend beyond a footprint of the package substrate. The second segment may extend vertically from the first segment and may extend at least partially through the at least one opening of the package substrate.Type: ApplicationFiled: October 18, 2022Publication date: April 25, 2024Inventors: Bok Eng CHEAH, Seok Ling LIM, Jenny Shio Yin ONG, Jackson Chung Peng KONG, Kooi Chi OOI
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Patent number: 11955431Abstract: Semiconductor packages, and methods for making the semiconductor packages, having an interposer structure with one or more interposer and an extension platform, which has an opening for placing the interposer, and the space between the interposer and the extension platform is filled with a polymeric material to form a unitary interposer-extension platform composite structure. A stacked structure may be formed by at least a first semiconductor chip coupled to the interposer and at least a second semiconductor chip coupled to the extension platform, and at least one bridge extending over the space that electrically couples the extension platform and the interposer. The extension platform may include a recess step section that may accommodate a plurality of passive devices to reduced power delivery inductance loop for the high-density 2.5D and 3D stacked packaging applications.Type: GrantFiled: August 7, 2020Date of Patent: April 9, 2024Assignee: Intel CorporationInventors: Jenny Shio Yin Ong, Seok Ling Lim, Bok Eng Cheah, Jackson Chung Peng Kong, Saravanan Sethuraman
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Patent number: 11942412Abstract: To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.Type: GrantFiled: October 13, 2020Date of Patent: March 26, 2024Assignee: Intel CorporationInventors: Bok Eng Cheah, Jackson Chung Peng Kong, Min Suet Lim, Tin Poay Chuah
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Publication number: 20240071934Abstract: The present disclosure is directed to semiconductor packages incorporating composite or hybrid bridges that include first and second interconnect bridges positioned on a substrate and a power corridor with a plurality of vertical channels positioned on the substrate between the first and second interconnect bridges, wherein the power corridor integrally joins the first interconnect bridge to the second interconnect bridge.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Inventors: Bok Eng CHEAH, Jenny Shio Yin ONG, Jackson Chung Peng KONG, Seok Ling LIM
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Publication number: 20240071856Abstract: The present disclosure is directed to an electronic assembly and method of forming thereof. The electronic assembly may include a substrate and a first die with first and second opposing surfaces. The first die may be coupled to the substrate at the first surface. At least one first trench may extend partially through the first die from the second surface. A stiffener may be attached to the substrate. The stiffener may have a cavity that accommodates the first die, in which the second surface of the first die faces the stiffener. A thermally conductive layer may be positioned between the stiffener and the first die. The conductive layer at least partially fills the at least one first trench.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventors: Bok Eng CHEAH, Seok Ling LIM, Jenny Shio Yin ONG, Jackson Chung Peng KONG, Kooi Chi OOI
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Patent number: 4089775Abstract: A process for simultaneously desulfurizing and dewaxing raw, untreated, high sulfur-containing wide-cut petroleum oil fractions to produce desulfurized middle distillate oils of low pour point with a minimum cracking of the raw fraction to gases which comprises contacting the raw fraction with hydrogen and a catalyst comprising a hydrogenating component and faujasite on an amorphous support. A particularly preferred catalyst consists of 95 wt.% based on total catalyst of NiO/MoO.sub.3 on an amorphous silica/alumina support and 5 wt.% of nickel-exchanged faujasite.Type: GrantFiled: December 27, 1976Date of Patent: May 16, 1978Assignee: Exxon Research & Engineering Co.Inventors: Dietmar Berger, Jackson Eng
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Patent number: 4054512Abstract: An asphalt-containing mineral oil is deasphalted by contacting the oil with a liquid hydrogen sulfide deasphalting solvent for a time sufficient to remove a substantial portion of the asphalt from the oil. Utilization of liquid hydrogen sulfide as the deasphalting solvent is capable of giving high yields of deasphalted oil. In contrast to the use of aliphatic solvents for deasphalting, the hydrogen sulfide readily mixes with the heavy feed even at relatively low temperatures.Type: GrantFiled: October 22, 1976Date of Patent: October 18, 1977Assignee: Exxon Research and Engineering CompanyInventors: John J. Dugan, Jackson Eng
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Patent number: 3997427Abstract: A process for hydrotreating middle distillate fraction petroleum feed stocks wherein hydrogen requirements for the hydrotreater are reduced by first passing the feed stock and steam to a steam hydroconversion zone over a dual function catalyst comprising molybdenum on a chromium supported on ferric oxide support or on a high surface area alumina support. In the steam hydroconversion zone a portion of the feed reacts with the steam to produce hydrogen via a steam reforming reaction. This hydrogen is used in situ to saturate a substantial portion of the olefins and remove some of the sulfur compounds present in the feed stock, thereby partially refining same. The partially refined feed is then passed to a hydrotreating zone for further treatment with greatly reduced hydrogen requirements in said hydrotreating zone.Type: GrantFiled: December 24, 1975Date of Patent: December 14, 1976Assignee: Exxon Research and Engineering CompanyInventors: Jackson Eng, Noel J. Gaspar